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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD invertor_IR

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Update time: 2021-05-10 21:14:57
Creation time: 2019-02-25 09:39:18
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ID Name Designator Footprint Quantity
1 1N4448 D2,D4,D5 DO-35 3
2 200R R1,R2 AXIAL-0.3 2
3 LOAD R3 AXIAL-0.3 1
4 100k R6 AXIAL-0.3 1
5 10k R7,R8,R9,R10 AXIAL-0.3 4
6 1u C1,C6,C9,C2,C3,C4 CAP-D3.0XF1.5 6
7 HCPL-3150-000E U2,U3 DIP-8 2
8 XFMR T2,T3,T4 NONE 3
9 1u C5,C11,C12 RAD-0.1 3
10 10n C7 RAD-0.1 1
11 1n C8 RAD-0.1 1
12 2W10 D1,D3,D6 BRIDGE-WOB 3
13 1k R4,R5,10R AXIAL-0.3 3
14 10 Om 10R AXIAL-0.3 1
15 IRF740 Q1,Q2 TO-220 2
16 ACS712ELCTR-30A-T U6 SOIC-8_150MIL 1
17 ARDUINO U4 ARDUINO-NODIM 1
18 IR2110PBF U1 DIP-14 1
19 TRANSFORMER_CENTRE_TAPPED_US T1 NONE 1

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