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2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
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1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD Bell Controller v.1
License: null
Mode: Editors' pick
ID | Name | Designator | Footprint | Quantity | BOM_Manufacturer Part |
---|---|---|---|---|---|
1 | 1K | R5 | 1206 | 1 | RT1206FRD071KL |
2 | 22pF | C2,C3 | 1206 | 2 | 0603N220G500 |
3 | 620 | R4 | 1206 | 1 | RCT03620RJLF |
4 | button/led | P2 | HDR-IDC-2.54-2X8P | 1 | IDC Box 2.54mm 16P Straight |
5 | 33Ω | R28 | 1206 | 1 | 1206W4J0330T5E |
6 | 2K | R2 | 1206 | 1 | RCT032KFLF |
7 | ATMEGA2560 | MAIN_CODE | TQFP-100_14X14X05P | 1 | ATMEGA2560-16AU |
8 | display resolution | T1 | RES-ADJ_3362P | 1 | 3362P-1-103LF |
9 | clock bell select | T2 | RES-ADJ_3362P | 1 | 3362P-1-103LF |
10 | 330 | R3 | 1206 | 1 | RCT03330RJLF |
11 | ICSP | S2 | HDR-3X2/2.54 | 1 | Header-Male-2.54_2x3 |
12 | lcd | CN1 | LCD_20X4 | 1 | RELIMATE CON 16 PIN |
13 | UART | S1 | HDR-3X2/2.54 | 1 | DS1023-2*3SF11 |
14 | 1N4001F | D1,D2,D3,D4,D5,D6 | SMAF | 6 | 1N4001F |
15 | signal/power | P1 | HDR-IDC-2.54-2X4P | 1 | IDC Box 2X4 2.54MM |
16 | 3.3k | R6 | 1206 | 1 | 0603WAF3301T5E |
17 | sel/man/clock button | P3 | HDR-IDC-2.54-2X10P | 1 | IDC Box 2.54mm 2X10P Straight |
18 | 10k | R1,R7,R8,R9,R10,R11,R19,R20,R21,R26,R27,R13,R12,R22,R23,R24,R25 | 1206 | 17 | CR0603JA0103G |
19 | 10KΩ(103) | R14,R15,R16,R17,R18 | 1206 | 5 | CR0603JA0103G |
20 | DS3231 | U4 | SOIC-16_300MIL | 1 | DS3231M+TRL |
21 | 100nF | C7,C6,C5,C4,C1,C8,C9,C12,C10 | 1206 | 9 | 06033C104KAT2A |
22 | 100uF | C11 | 1206 | 1 | 06033C104KAT2A |
23 | 16MHz | X1 | HC-49S | 1 | E49A16E00000KE10CO |
24 | LD1117S12TR | U1 | SOT-223 | 1 | LD1117S12TR |
25 | BS-2-1 | CR2032_BATTERY | BATTERY-1 | 1 | BS-2-1 |
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