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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD Project_driver_v2

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Update time: 2020-03-26 03:34:40
Creation time: 2020-03-25 12:12:57
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ID Name Designator Footprint Quantity
1 IR2101STRPBF U3,U2,U1 SOIC-8_L5.0-W4.0-P1.27-LS6.0-BL 3
2 1N4148WS D3,D2,D1 SOD-323_L1.8-W1.3-LS2.5-RD 3
3 100 R6,R5,R4,R3,R2,R1,R8 AXIAL-0.3 7
4 MP2307DN-LF-Z U4 SOP-8_L4.9-W3.9-P1.27-LS6.0-BL-EP 1
5 FC-D1608UGK-520D10 LED1 LED0603-FD 1
6 10uH L1 AXIAL-0.4 1
7 10u C6,C4,C1 RAD-0.1 3
8 2.2u C5,C3,C2 RAD-0.1 3
9 IRLR7843TRPBF Q6,Q5,Q4,Q3,Q2,Q1 TO-252-2_L6.5-W6.1-P4.58-LS10.0-BR 6
10 Header-Male-2.54_1x1 P1,P2 HDR-1X1/2.54 2
11 6.8k R7 AXIAL-0.3 1
12 100k R9 AXIAL-0.3 1
13 10k R10 AXIAL-0.3 1
14 44.2k R11 AXIAL-0.3 1
15 22uF C7,C8,C9,C10,C11,C12,C13 RAD-0.1 7
16 10n C14 RAD-0.1 1
17 100n C15 RAD-0.1 1
18 3.9n C16 RAD-0.1 1
19 10uF C17 RAD-0.1 1

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