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Standard

1.Easy to use and quick to get started

2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

Profession

1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

4.For enterprises, more professional users

Ongoing

STD klavakoka

License: Public Domain

Mode: Editors' pick

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Update time: 2021-06-28 15:10:30
Creation time: 2020-06-10 10:20:28
Description
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Design Drawing
schematic diagram
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ID Name Designator Footprint Quantity
1 rrrrrr U8 SOIC-9_L5.0-W4.0-P1.00-LS6.2-BL 1
2 RESONATOR_NOCAP XTAL1 RESONATOR_NOCAP 1
3 10mkF C17 CAP-TH_BD8.0-P3.50-D1.0-FD 1
4 NDiode2 LED3,LED1,LED2 SOD-123_L2.8-W1.8-LS3.7-FD 3
5 JUMPER JP2 JUMPER2 1
6 33pF C9,C1,C10 C0201 3
7 10pF C6,C2 C0201 2
8 0.1mkF C7,C3,C4,C5,C8,C11,C12,C15,C13,C14 C0201 10
9 SN74LS174DR U4 SOIC-16_L9.9-W3.9-P1.27-LS6.0-BL 1
10 LM7805L-TF3-T Q1 TO-220F-3_L10.2-W4.9-P2.54-L 1
11 Jumper_NC_Dual JP1 JUMPER3 1
12 rrr U7 DIO-BG-SMD_SOIC-4 1
13 CD4 U2,U3 SOIC-16_L10.8-W5.5-P1.27-LS7.8-BL 2
14 F1 SW1,SW54 SW-TH_SPVQ810502 2
15 SYS REG SW2 SW-TH_SPVQ810502 1
16 F5 SW3 SW-TH_SPVQ810502 1
17 F6 SW4 SW-TH_SPVQ810502 1
18 F9 SW5 SW-TH_SPVQ810502 1
19 F10 SW6 SW-TH_SPVQ810502 1
20 F2 SW7 SW-TH_SPVQ810502 1
21 PBI SC SW8 SW-TH_SPVQ810502 1
22 ESC SW9 SW-TH_SPVQ810502 1
23 TAB SW10 SW-TH_SPVQ810502 1
24 F4 SW11 SW-TH_SPVQ810502 1
25 F7 SW12 SW-TH_SPVQ810502 1
26 F8 SW13 SW-TH_SPVQ810502 1
27 F3 SW15 SW-TH_SPVQ810502 1
28 1 END SW22 SW-TH_SPVQ810502 1
29 2 DOWN SW20 SW-TH_SPVQ810502 1
30 4 LEFT SW19 SW-TH_SPVQ810502 1
31 5 SW18 SW-TH_SPVQ810502 1
32 7 HOME SW17 SW-TH_SPVQ810502 1
33 8 UP SW16 SW-TH_SPVQ810502 1
34 NUM LOCK SW14 SW-TH_SPVQ810502 1
35 - SW21 SW-TH_SPVQ810502 1
36 9 PGUP SW23 SW-TH_SPVQ810502 1
37 + SW24 SW-TH_SPVQ810502 1
38 6 RIGHT SW25 SW-TH_SPVQ810502 1
39 3 PGDN SW26 SW-TH_SPVQ810502 1
40 Scroll Lock SW27 SW-TH_SPVQ810502 1
41 LEFT SW29 SW-TH_SPVQ810502 1
42 : \ SW28 SW-TH_SPVQ810502 1
43 ENTER SW30 SW-TH_SPVQ810502 1
44 ' SW31 SW-TH_SPVQ810502 1
45 + = SW39 SW-TH_SPVQ810502 1
46 ) ] SW38 SW-TH_SPVQ810502 1
47 ( [ SW37 SW-TH_SPVQ810502 1
48 = SW36 SW-TH_SPVQ810502 1
49 DEL SW35 SW-TH_SPVQ810502 1
50 0 INS SW34 SW-TH_SPVQ810502 1
51 - _ SW33 SW-TH_SPVQ810502 1
52 SPACE SW32 SW-TH_SPVQ810502 1
53 > . SW40 SW-TH_SPVQ810502 1
54 ( 9 SW41 SW-TH_SPVQ810502 1
55 ? / SW42 SW-TH_SPVQ810502 1
56 L SW43 SW-TH_SPVQ810502 1
57 : ; SW44 SW-TH_SPVQ810502 1
58 O SW45 SW-TH_SPVQ810502 1
59 P SW46 SW-TH_SPVQ810502 1
60 ) 0 SW47 SW-TH_SPVQ810502 1
61 * 8 SW55 SW-TH_SPVQ810502 1
62 U SW53 SW-TH_SPVQ810502 1
63 K SW52 SW-TH_SPVQ810502 1
64 J SW51 SW-TH_SPVQ810502 1
65 < , SW50 SW-TH_SPVQ810502 1
66 & 7 SW49 SW-TH_SPVQ810502 1
67 M SW48 SW-TH_SPVQ810502 1
68 B SW56 SW-TH_SPVQ810502 1
69 % 5 SW57 SW-TH_SPVQ810502 1
70 N SW58 SW-TH_SPVQ810502 1
71 G SW59,SW71 SW-TH_SPVQ810502 2
72 H SW60 SW-TH_SPVQ810502 1
73 T SW61 SW-TH_SPVQ810502 1
74 I SW62 SW-TH_SPVQ810502 1
75 ^ 6 SW63 SW-TH_SPVQ810502 1
76 ! 1 SW64,SW78 SW-TH_SPVQ810502 2
77 R SW65 SW-TH_SPVQ810502 1
78 E SW66 SW-TH_SPVQ810502 1
79 F SW67 SW-TH_SPVQ810502 1
80 D SW68 SW-TH_SPVQ810502 1
81 V SW69 SW-TH_SPVQ810502 1
82 # 3 SW70 SW-TH_SPVQ810502 1
83 Z SW79 SW-TH_SPVQ810502 1
84 X SW77 SW-TH_SPVQ810502 1
85 A SW76 SW-TH_SPVQ810502 1
86 S SW75 SW-TH_SPVQ810502 1
87 Q SW74 SW-TH_SPVQ810502 1
88 W SW73 SW-TH_SPVQ810502 1
89 @ 2 SW72 SW-TH_SPVQ810502 1
90 CTRL SW84 SW-TH_SPVQ810502 1
91 CAPS LOCK SW83 SW-TH_SPVQ810502 1
92 ALT SW82 SW-TH_SPVQ810502 1
93 SHIFT (L) SW81 SW-TH_SPVQ810502 1
94 SHIFT (R) SW80 SW-TH_SPVQ810502 1
95 RP3 R150,R100,R200,R250 R2512 4
96 1N4148 D2,D1,D6,D4,D3,D5,D7 DO-35_BD2.0-L4.0-P8.00-D0.5-FD 7
97 150 R8,R1,R2,R3,R4,R5,R6,R7 R0201 8
98 10k R10,R9 R0201 2
99 640445-7 U1 CONN-TH_7P-P3.96_L7.6-W27.7 1
100 cpu U5 SOIC-50_L27.8-W7.3-P1.02-LS10.7-BL 1
101 K7407US U6 SDIP-10_L9.6-W6.6-P1.77-LS7.6-BL 1
102 asd U10 SOIC-9_L5.0-W4.0-P1.00-LS6.2-BL 1

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