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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD Faruh_Mirror

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Update time: 2022-10-19 20:32:49
Creation time: 2021-06-15 18:32:24
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ID Name Designator Footprint Quantity
1 0.1uF C1,C3 C0805 2
2 0.33uF C2 C0805 1
3 S9B-PH-SM4-TB(LF)(SN) CN2 S9B-PH-SM4-TB(LF)(SN) 1
4 M7 D1 M7. 1
5 BC817 Q1,Q2 SOT-23-3_L2.9-W1.3-P1.90-LS2.4-BR 2
6 10k R1,R2,R5,R6,R9,R10,R13 R1206 7
7 330k R3,R7,R11 R1206 3
8 220k R4,R8,R12 R1206 3
9 3.3k R14,R16 R1206 2
10 100 R15,R17 R0805 2
11 ATTINY25V-10S U1 SOIC8_EIAJ_208MIL 1
12 78L05_C411012 U2 SOT-89-3_L4.5-W2.5-P1.50-LS4.2-BR 1

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