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Jmter NOR flip-flop-problem

3 years ago 450
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Description

Two ways to start up a NOR flip-flop circuit.

Using a ramped VDD supply or the UIC command appears to work for most cases but can be defeated by having the S and R signals being identical (i.e. del1 and del2 are integer multiples of 'tp').

Using a constant VDD supply without the UIC command appears to work but only for negative values of del1 and del2 (that are also not integer multiples of 'tp').

I suspect that the problem here is that when the two gates are enabled at the same time, their outputs can start up in a metastable state and so can oscillate at a period of twice the individual gate propagation delay.

Documents

anf 2 square delayed with uic

anf 2 square delayed with ramped VDD

anf 2 square delayed with constant VDD and no uic

BOM

ID Name Designator Quantity
1 PULSE({lo} {hi} {del2} {tr} {tr} {ton} {tp}) V2 1
2 PULSE({lo} {hi} {del1} {tr} {tr} {ton} {tp}) V1 1
3 {vdd} V3 1
4 NOR2EE U1,U2 2
5 PULSE(0 {vdd}) V3 1

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