There are 4 problems with this simulation. 1) When first running it there is a fatal error saying that the ADA4700 has missing nodes.  2) Inspecting the netlist shows that no subckt for the ADA4700 has been pulled into the netlist; 3) Inspecting the netlist shows that the subckt for the UA741 has been pulled into the netlist 4) The statement: **.inc ADI1.lib ** has been added to the netlist but if the netlist is run in native LTspice, this statement has to be changed to: **.lib ADI.lib** before the AD823 model is found. ``` ** Sheet_1 ** XU1 IN OUT +5V GND OUT AD823 V1 IN GND SINE(2.5 2.5 1.5MEG) V445 +5V GND +5V .SAVE OUT IN .tran 1.2u * UA741 OPERATIONAL AMPLIFIER \"MACROMODEL\" SUBCIRCUIT * CREATED USING PARTS RELEASE 4.01 ON 07/05/89 AT 09:09 * (REV N/A) SUPPLY VOLTAGE: +/-15V * CONNECTIONS: NON-INVERTING INPUT * | INVERTING INPUT * | | POSITIVE POWER SUPPLY * | | | NEGATIVE POWER SUPPLY * | | | | OUTPUT * | | | | | .SUBCKT UA741 1 2 3 4 5 * C1 11 12 4.664E-12 C2 6 7 20.00E-12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY(2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY(5) VB VC VE VLP VLN 0 10.61E6 -10E6 10E6 10E6 -10E6 GA 6 0 11 12 137.7E-6 GCM 0 6 10 99 2.574E-9 IEE 10 4 DC 10.16E-6 HLIM 90 0 VLIM 1K Q1 11 2 13 QX Q2 12 1 14 QX R2 6 9 100.0E3 RC1 3 11 7.957E3 RC2 3 12 7.957E3 RE1 13 10 2.740E3 RE2 14 10 2.740E3 REE 10 99 19.69E6 RO1 8 5 150 RO2 7 99 150 RP 3 4 18.11E3 VB 9 0 DC 0 VC 3 53 DC 2.600 VE 54 4 DC 2.600 VLIM 7 8 DC 0 VLP 91 0 DC 25 VLN 0 92 DC 25 .MODEL DX D(IS=800.0E-18) .MODEL QX NPN(IS=800.0E-18 BF=62.50) .ENDS .inc ADI1.lib ```