© 2024 EasyEDA Some rights reserved ISO/IEC
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD Netflag problems in simulations.
License: Public Domain
Mode: Editors' pick
In answering this topic:
https://easyeda.com/forum/topic/voltage-source-simulation-pcb-implementation-dabdd889176c4cb2a7de722c3031bb9e
it has been found that there are problems with the internal voltage sources that EasyEDA auto-assigns to simulations when netflags such as VCC, +5V are assigned to nets.
It looks like as long as any other explicitly placed voltage source in the sim does not share a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source then all the voltage sources are netlisted correctly.
However, if any other explicitly placed voltage source in the sim does share a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source then some or all the voltage sources are not netlisted correctly.
Sheets Sheet_ to Sheet_4 in this project demonstrate this issue by pasting the netlists into the schematics as text.
Sheet_1
Open in EditorSheet_2
Open in EditorSheet_4
Open in EditorSheet_3
Open in EditorSheet_5
Open in EditorSheet_7
Open in EditorSheet_6
Open in EditorID | Name | Designator | Footprint | Quantity |
---|---|---|---|---|
1 | 1K | R11,R10,R1,R2,R5,R6,R4,R3,R7,R8,R13,R14,R9,R12 | AXIAL-0.3 | 14 |
2 | 1 | V1,V3,V2,V4,V7 | HDR1X2 | 5 |
3 | 5 | V5,V6 | HDR1X2 | 2 |
Unfold
Loading...
Do you need to add this project to the album?