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STD Netflag problems in simulations.

License: Public Domain

Mode: Editors' pick

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Update time: 2021-02-25 14:53:59
Creation time: 2021-02-25 13:13:30
Description

In answering this topic:

 

https://easyeda.com/forum/topic/voltage-source-simulation-pcb-implementation-dabdd889176c4cb2a7de722c3031bb9e

 

it has been found that there are problems with the internal voltage sources that EasyEDA auto-assigns to simulations when netflags such as VCC, +5V are assigned to nets.

 

  • This causes this simulation to be produce rubbish results which was not noticed by the user as they are a self-confessed novice.

 

It looks like as long as any other explicitly placed voltage source in the sim does not share a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source then all the voltage sources are netlisted correctly

 

However, if any other explicitly placed voltage source in the sim does share a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source then some or all the voltage sources are not netlisted correctly

 

Sheets Sheet_ to Sheet_4 in this project demonstrate this issue by pasting the netlists into the schematics as text.

 

  • Until this issue has been resolved it is recommended that all reqired voltage sources MUST be placed explicitly in the schematic as shown in Sheet_5 to correctly netlist all voltage sources. Voltage sources can then be connected to other nodes using netflags without the netflags invoking additional EasyEDA auto-assigned voltage sources.

 

 

Design Drawing
schematic diagram
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PCB
1 /
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ID Name Designator Footprint Quantity
1 1K R11,R10,R1,R2,R5,R6,R4,R3,R7,R8,R13,R14,R9,R12 AXIAL-0.3 14
2 1 V1,V3,V2,V4,V7 HDR1X2 5
3 5 V5,V6 HDR1X2 2

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