License

GPL 3.0

Tags
Recommend Projects

VGA with RAM

1 year ago 296
  • Description
  • Documents
  • BOM
  • Attachments
  • Members
  • Comments

Description

A VGA card add-on for Warren Toomey's CSCvon8

Documents

Count and Control

Bus and Logic

VGA

PCB_2021-01-26_21-55-12

BOM

ID Name Designator Footprint Quantity
1 Pwr + Ctrl H3 HDR-F-2.54_1X6 1
2 68 R7,R8 RES-TH_BD2.4-L6.3-P10.30-D0.6 2
3 74HCT574 Pixel reg U14 DIP20 1
4 DM74LS574N Pixel U9 DIP20 1
5 DM74LS574N Background U19 DIP20 1
6 74HCT574 X coord reg U13 DIP20 1
7 74HCT574 Y coord reg U12 DIP20 1
8 71256SA15TPG Alt Video mem U21 DIP28-300 1
9 71256SA15TPG Video mem U11 DIP28-300 1
10 1.5K R3,R5,R1 RES-TH_BD2.3-L6.5-P10.50-D0.5 3
11 100n C4,C5,C6,C8,C9,C20,C3,C10,C2,C7,C16,C22,C21,C1,C19,C18,C17,C15,C14,C12,C11 RAD-0.1 21
12 Data Bus H2 HDR-F-2.54_1X8 1
13 74HCT04 Inverter U15 DIP-14_L19.0-W7.0-P2.54-LS7.6-BL 1
14 74HCT161 Y count low U4 DIP16 1
15 74HCT161 Y count high U6 DIP16 1
16 74HCT161 Y count mid U5 DIP16 1
17 74HCT161 X count high U3 DIP16 1
18 74HCT161 X count low U2 DIP16 1
19 74HCT32 OR U16 DIP-14_L19.0-W7.0-P2.54-LS7.6-BL 1
20 27.175MHz X1 OSCILLATOR_DIP-14 1
21 39SF010 Pixel Control ROM U18 DIP32-600 1
22 39SF010 Control ROM U7 DIP32-600 1
23 750 R6,R4,R2 RES-TH_BD2.2-L6.5-P10.50-D0.6 3
24 1-1734530-3 DSUB1 DSUB-15P-22.0X30.8-H12.5-TE 1
25 2.1MMJACKTHM U20 PJ-102A 1
26 74HCT163 Master clock U1 DIP16 1
27 Address Bus H1 HDR-F-2.54_1X16 1
28 74HCT245 X count buffer U10 DIP-20_L25.5-W10.0-P2.54-LS7.6-BL 1
29 74HCT245 Y count buffer U8 DIP-20_L25.5-W10.0-P2.54-LS7.6-BL 1
30 SN74LS173AN U17 DIP16 1

Attachments

None
Success
The owner does not allow comments in this project now

Comments (0)

goToTop
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow