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Easy logic device simulation in V2.3.x onwards

4 years ago 3201
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Description

Some simple test jigs to demonstrate the EasyEDA logic family spice models.

Documents

DFFEE D type flip flop demo

EasyEDA logic family demo

74HC4060EE symbol with model external clocked test jig

HALF74HC74EE schematic test jig

74HC74EE symbol with model test jig

74HC93EE symbol with model test jig

74HC4060EE symbol with model RC clocked test jig

74HC4060EE symbol with model crystal clocked test jig

74HC73EE symbol with model test jig

74HC112EE symbol with model test jig

74HC390EE symbol with model test jig

74HC4040EE symbol with model test jig

74HC4020EE symbol with model test jig

CD4049 hex inverter test jig with symbol using INVEE subckts

INVEE test jig with symbol

NAND2EE test jig with symbol

AND2EE test jig with symbol

OR2EE test jig with symbol

NOR2EE test jig with symbol

NAND3EE test jig with symbol

AND3EE test jig with symbol

OR3EE test jig with symbol

NOR3EE test jig with symbol

XOR2EE test jig with symbol

SCHMITTINVEE test jig with symbol

SCHMITTNAND2EE gated oscillator test jig with symbol

SCHMITTEE test jig with symbol

BUFFEE test jig with symbol

XNOR2EE test jig with symbol

CD4001 quad nor test jig with symbol.

74HC04 hex inverter test jig

74HC05 open drain output hex inverter test jig

BUFFTSEE symbol test jig: with hidden supply pins.

BUFFTSEE symbol test jig: with visible supply pins

INVEE test jig2 with symbol pins hidden.

INVEE test jig2 with symbol pins visible.

About the EasyEDA logic devices

74HC123EE symbol with model test jig

BOM

ID Name Designator Footprint Quantity Manufacturer Part Manufacturer Supplier Supplier Part Price LCSC Assembly Mounted
1 {vcc} V1 2P-5.0 1
2 PULSE(0 {vcc} 1.5u {tedge} {tedge} 0.1u 1u) VCLK1 2P-5.0 1
3 PULSE(0 {vcc} 100n {tedge} {tedge} 0.1u ) VSET1 2P-5.0 1
4 PULSE(0 {vcc} 500n {tedge} {tedge} 0.1u ) VRESET1 2P-5.0 1
5 1k R1,R2,R4,R3,R5,R6 R3 6
6 DFFEE U1,U8 DIP 2
7 SINE({vcc} 0.5 50k 0 0 180) V1 2P-5.0 1
8 JKFFEE U6 DIP 1
9 NMOS_E M4 1
10 1Meg R3 R3 1
11 10p C1 1206 1
12 XNOR2EE U4,U1 2
13 {vcc} AC 1 0 V1 2P-5.0 1
14 PULSE(0 {vcc} 0 {tedge} {tedge} 0.5u 1u) AC 1 0 VCLK 2P-5.0 1
15 PULSE(0 {vcc} 10u {tedge} {tedge} 0.1u) VMR 2P-5.0 1
16 100k R1,R2,RT1,RSER R3 4
17 5p C1,C2 1206 2
18 74HC4060EE U1,U3 DIP 2
19 PULSE(0 3.3 100n 10n 10n 490n 1u) V1 2P-5.0 1
20 3.3 V2 2P-5.0 1
21 1n C3,C1,C2 1206 3
22 HALF74HC74EE U2 DIP 1
23 PULSE(0 {VCC} 1u 10n 10n 1u 2u) V1 2P-5.0 1
24 PULSE(0 {VCC} 100n) V2 2P-5.0 1
25 74HC74EE U2 DIP 1
26 74HC93EE U3 DIP 1
27 PULSE(0 {vcc} 0 1u) V1 2P-5.0 1
28 470k RSER R3 1
29 100p CT1,CT2,C1 1206 3
30 2.2k RT1 R3 1
31 30p CT1 1206 1
32 XTALfast Q1 1X02 1
33 74HC73EE U3 DIP 1
34 74HC112EE U2 DIP 1
35 15n C1 1206 1
36 74HC390EE U2 DIP 1
37 74HC4040EE U2 DIP 1
38 PULSE(0 {vcc} 45u {tedge} {tedge} 0.1u) VMR 2P-5.0 1
39 74HC4020EE U1 DIP 1
40 PULSE(0.5 4.5 0 100n 100n 400n 1000n) AC 1 0 V1 2P-5.0 1
41 5 V2 BATTERY 1
42 200p C1 1206 1
43 CD4049EE U4 DIP 1
44 SIN(2.5 8 1Meg 0 0 -90) V1 1
45 SINE(5 2 100k) VDD 1
46 1k RSOURCE,RLOAD,RSOURCE2,RSOURCE1,RSOURCE3 0603 5
47 INVEE U1,U3 DIP 2
48 PULSE(-1 5 2.5u 10n 10n 1u 2u) V2 1
49 PULSE(-1 5 0 10n 10n 1u 2u) V1 1
50 NAND2EE U1 DIP 1
51 AND2EE U1 DIP 1
52 OR2EE U1 DIP 1
53 0 VNETLINK 1
54 NOR2EE U4 DIP 1
55 PULSE(-1 5 2.5u 10n 10n 4u 8u) V3 1
56 NAND3EE U1 DIP 1
57 AND3EE U1 DIP 1
58 OR3EE U1 DIP 1
59 NOR3EE U1 DIP 1
60 XOR2 U4 1
61 SIN(2.5 4 1Meg) V1 1
62 SCHMITTINVEE U2 DIP 1
63 5 VDD 1
64 470p COSC 1206 1
65 4.7k ROSC 0603 1
66 PULSE(0 5 2u 100n 100n 15u) V1 1
67 SCHMITTNAND2EE U2 DIP 1
68 SCHMITTEE U2 DIP 1
69 BUFFEE U2 DIP 1
70 PULSE(0 5 0 100n 100n 400n 1000n) AC 1 0 V1 2P-5.0 1
71 PULSE(4.5 0.5 2.2u 100n 100n 4.9u) AC 1 0 V3 2P-5.0 1
72 CD4001EE U10 DIP 1
73 74HC04EE U2 DIP14 1
74 74HC05EE U1 DIP14 1
75 pulse(0 5 0 40n 40n 460n 1u) V1 2P-5.0 1
76 pulse(0 5 0.75u 40n 40n 2u) V2 2P-5.0 1
77 5 V3 2P-5.0 1
78 BUFFTSEE U1 DIP 1
79 PULSE(0 {Vrail} 0 10n 10n 490n 1u) V1 1
80 {Vrail} VDD 1
81 {VDD} VDD 2P-5.0 1
82 2k R2 R3 1
83 60n C1 1206 1
84 800n C2 1206 1
85 PULSE({VDD} 0 0.5m {tedge} {tedge} 10u 9m) VRESET 2P-5.0 1
86 PULSE(0 {VDD} 1m {tedge} {tedge} 10u 2m) VTRIG 2P-5.0 1
87 74HC123EE U2 DIP 1

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