© 2024 EasyEDA Some rights reserved ISO/IEC
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD PLCA_TESIS_01
License: Public Domain
Mode: Editors' pick
ID | Name | Designator | Footprint | Quantity |
---|---|---|---|---|
1 | POT | RV1,RV2,RV3 | POT_ALPHA_RV16AF-20 | 3 |
2 | TL072CN | U1 | DIP-8_L9.4-W6.4-P2.54-LS9.1-BL | 1 |
3 | bornier 3P | U3,U5,U6 | BORNIER 3P | 3 |
4 | BORNIER_5.08_2P COPY | U2,U4 | BORNIER_5.08_2P | 2 |
5 | 1000uF | C1,C2,C3,C4 | CAP-TH_BD10.0-P5.00-D1.0-FD | 4 |
6 | 5.1K | R1 | RES-TH_BD3.3-L9.0-P13.00-D0.6 | 1 |
7 | 100 | R2,R3 | RES-TH_BD3.3-L9.0-P13.00-D0.6 | 2 |
Unfold
Loading...
Do you need to add this project to the album?