© 2024 EasyEDA Some rights reserved ISO/IEC
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
STD 9P_DCELL_Pack
Mode: Editors' pick
Cloned from BatteryPack
PCB_2020-03-27 10:29:34
Open in EditorPCB_2020-03-27 12:20:19
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Open in EditorID | Name | Designator | Footprint | Quantity |
---|---|---|---|---|
1 | 2920L150DR | FUSE1 | F2920 | 1 |
2 | BSC028N06NSATMA1 | Q2 | PG-TDSON-8_L5.0-W6.0-P1.27-LS6.2-BL-EP | 1 |
3 | SI2347DS-T1-GE3 | Q1 | SOT-23_L2.9-W1.3-P0.95-LS2.4-BR | 1 |
4 | Header-Male-2.54_1x1 | P1,P2,P3,P4,P5,P6,P7,P8,P22,P9,P10,P11 | HDR-1X1/2.54 | 12 |
5 | LM74610QDGKTQ1 | U1 | VSSOP-8_L3.0-W3.0-P0.65-LS5.0-BL | 1 |
6 | 1k | R1 | 1206 | 1 |
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