Editor Version ×
Standard

1.Easy to use and quick to get started

2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

Profession

1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

4.For enterprises, more professional users

Ongoing

STD TPS70151 Dual-Output LDO Voltage Regulators

License:

Mode: Editors' pick

  • 1.1k
  • 0
  • 0
Update time: 2021-04-11 20:30:55
Creation time: 2015-11-21 13:58:41
Description
Dual-Output Low Dropout Voltage Regulator switch Power-Up Sequencing for Split-Voltage DSP Systems. **Features:** Dual Output Voltage for Split-supply Applications Selectable Power-up Sequencing for DSP Application Output Current Range of 500mA on Regulator 1 and 250mA on Regulator2 Fast Transient Response Open Drain Power-On Reset with 120ms Delay Open Drain Power Good for Regulator 1 Ultra Low 190mA (typ) Quiescent Current 1mA Input Current During Standby Low Noise: 65mVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature Two Manual Reset Inputs 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature Thermal Shutdown Protection **Description** TPS701xx family devices are designed to provide a complete power management solution for the TMS320 DSP family, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes the TPS701xx family ideal for any TMS320 DSP applications with power sequencing requirements. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and an enable function, provide a complete system solution. The TPS701xx family of voltage regulators offer very low dropout voltage and dual outputs with power-up sequence control, which is designed primarily for DSP applications. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10µF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable/adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN (enable) shuts down both regulators, reducing the input current to 1µA at TJ = +25°C. The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins, respectively. The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (for example, an overload condition), VOUT1 is turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pull-up current source. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage conditions at VOUT1, which can be used to implement an SVS for the circuitry supplied by regulator 1. The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET output initiates a reset in DSP systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of VOUT2 and both manual reset pins (MR1 and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET goes to a high impedance state after a 120ms delay. RESET goes to the logic low state when the VOUT2 regulated output voltage is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V.
Design Drawing
schematic diagram
1 /
PCB
1 /
The preview image was not generated, please save it again in the editor.
ID Name Designator Footprint Quantity
1 TPS70151PWP U1 NONE 1
2 1u C1,C2,C3,C4 CP_8X13MM 4
3 SIP4 P1 HDR1X4 1

Unfold

Project Attachments
Empty
Project Members
Target complaint
Related Projects
Change a batch
Loading...
Add to album ×

Loading...

reminder ×

Do you need to add this project to the album?

服务时间

周一至周五 9:00~18:00
  • 0755 - 2382 4495
  • 153 6159 2675

服务时间

周一至周五 9:00~18:00
  • 立创EDA微信号

    easyeda

  • QQ交流群

    664186054

  • 立创EDA公众号

    lceda-cn