Combined sample-hold (SH) and peak detector (PD) for measuring the amplitude of ultra-fast (few ns) pulses originating e.g. from SiPMs or PMTs. The PCB is designed as plug-on board for the [MuonPi base PCB](https://easyeda.com/hgzaunick/cosmic_shower_detector_v1-52b8a2536bb6468e9f48412a774951d0_copy_copy) (version 3.0 or higher). The PCB is laid out as 2-layer board for rapid prototyping. The SH stage has two different gains (low/high gain selection from base PCB). The input to the SH stage is decoupled and dumped through a forward-biased Schottky barrier diode (MMBD770 or similar; the important parameter here is a very low minority-carrier lifetime yielding ultra-fast switch on/off times) onto an integration capacitor. The capacitor's voltage is buffered by an opamp with low input bias current, amplified and actively low- and high-pass filtered. The selected opamp is an inexpensive GBP=100 MHz quad opamp TLV3544 (TI). The PD part utilizes the remaining two opamps to drive the storage capacitor through a network of fast Schottky diodes and to isolate this capacitor with its ultra-high input impedance to avoid droop. Furthermore, two n-MOSFETs offer a fast reset of the storage cap (t_r>=100ns). Due to the symmetric design of this reset network, the MOSFET's gate-charge injection into the storage cap should be compensated. **Note:** This design was tested and several issues were found. Please refer to the [bugfixed and updated design version 2](https://easyeda.com/hgzaunick/muonpi-analog-pulse-processor-plug-on-board-v2).