A peak detector (PD) for measuring the amplitude of ultra-fast (few ns) pulses originating e.g. from SiPM or PMT photo detectors used in nuclear and particle physics. The PCB is designed as plug-on board for the MuonPi base PCB (version 3.0 or higher). The PCB is laid out as 2-layer board for rapid prototyping. The amplification has two different gains (low/high gain selection from base PCB).
The input to the first sample-hold (SH) stage is decoupled and dumped through a forward-biased Schottky barrier diode (MMBD770 or similar; the important parameter here is a very low minority-carrier lifetime yielding ultra-fast switch on/off times) onto an integration capacitor. The capacitor's voltage is buffered by an opamp with low input bias current, amplified and low-pass filtered. The selected opamp is an inexpensive GBP=100 MHz quad opamp TLV3544 (TI). This stage translates the short ns pulse into pulses with decay time in the us range without decreasing the amplitude by the same amount, as would be the case for a simple low-pass filter.
The second part, which is the actual peak detector (PD) utilizes the remaining three opamps to drive the storage capacitor through a network of fast Schottky diodes and to isolate this capacitor with its ultra-high input impedance to avoid droop (drain of the capacitor charge due to leakage). Furthermore, two n-MOSFETs offer a fast reset of the storage cap (t_r>=100ns). Droop is further reduced by bootstrapping the potentials at the pins of the second series diode and drain and source potential of the high-side MOSFET of the reset switch circuitry and thus nulling leakage through these components. With this last stage the pulse amplitude is clamped and held indefinetely to provide a sampling/digitization at low rates and speed until a reset pulse is applied.
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