© 2024 EasyEDA Some rights reserved ISO/IEC
Editor Version
×
Standard
1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
Profession
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
4.For enterprises, more professional users
Ongoing
STD LTC6994-1 and LTC6993-1 (hsync) Timing delay circuit
Mode: Editors' pick
- 0
Update time：
2021-04-09 21:08:00
Creation time：
2017-12-26 19:03:05
Description
Ill put notes on the schematic
Design Drawing
schematic diagram
（
1
/
）
PCB
（
1
/
）
The preview image was not generated, please save it again in the
editor.
| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | LTC6994CS6-1TRMPBF | U2 | TSOT-23-6_MK06A_HANDSOLDERING | 1 |
| 2 | LTC6993CS6-1TRMPBF | U1 | TSOT-23-6_MK06A_HANDSOLDERING | 1 |
| 3 | 976k | R1 | R0603 | 1 |
| 4 | 102k | R2 | R0603 | 1 |
| 5 | Header-Male-2.54_1x1 | HSIN,VSIN,P2,P3,P4,P5 | HDR-1X1/2.54 | 6 |
| 6 | 1k | R4,R3 | R0603 | 2 |
| 7 | csync | P1 | HDR-1X1/2.54 | 1 |
| 8 | 330 | R5 | R0805 | 1 |
| 9 | CS TTL | JP1 | SJ_2S | 1 |
| 10 | 74AHCT1G86SE-7 | U3 | SOT-353 | 1 |
| 11 | 1u | C1,C2,C3 | C0603 | 3 |
Unfold
Project Members
0
0
Collect to album
Target complaint
Related Projects
Change a batch
Loading...
Add to album
×
Loading...
reminder
×
Do you need to add this project to the album?