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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

Profession

1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD Jose V2

License: Public Domain

Mode: Editors' pick

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Update time: 2021-10-07 01:50:18
Creation time: 2021-07-30 23:24:03
Description

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Design Drawing
schematic diagram
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PCB
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ID Name Designator Footprint Quantity
1 RS485 TO TTL B1 RS485 TO TTL_2 1
2 470uF C1 CAP-D6.3XF2.5 1
3 0.1uF C2 CERAMIC CAPACITOR_100NF 1
4 display DISPLAY1,DISPLAY2,DISPLAY3,DISPLAY4 7 SEGMENT DISPLAY INVERTIDO 4
5 DC-005-2.0 J1 DC-IN-TH_DC-005-2.0 1
6 R1 R1 RESISTOR VERTICAL 1
7 R2 R2 RESISTOR VERTICAL 1
8 R3 R3 RESISTOR VERTICAL 1
9 R4 R4 RESISTOR VERTICAL 1
10 330R R5,R6,R7,R9,R10,R11,R12,R13,R14,R15,R17,R18,R19,R20,R21,R22,R23,R25,R26,R27,R28,R29,R30,R31 RESISTOR VERTICAL 24
11 1K R8 RES-TH_BD2.4-L6.3-P10.30-D0.6 1
12 470R R16 RESISTOR VERTICAL 1
13 10K R33 RES-TH_BD2.4-L6.3-P10.30-D0.6 1
14 10k R34,R35,R36,R37 SIP9 4
15 ESP32 U1 ESP32_DEVELOPMENT_KIT 1
16 ETHERNET U3 WIZNET_W5500 1
17 TERMINAl U4 CONN-TH_2EDGRC-5.08-04P-14-100A-H 1
18 MCP23S17 U6,U7 MCP23S17 MODULE 2
19 Regulador de Tensão LM2596 U8 REGULADOR DE TENSÃO LM2596 1
20 ULN2803APG ULN1,ULN2,ULN3,ULN4 DIP-18_L23.0-W6.5-P2.54-LS7.6-BL 4

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