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1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
Profession
1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
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STD Backplane_full_formated_v1
Mode: Editors' pick
- 0
Update time：
2021-01-11 20:36:10
Creation time：
2019-03-15 15:00:37
Description
Pensado para que coincida con las otras placas "formated"
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | GPIO0 | P8 | HDR-1X2/2.54 | 1 |
| 2 | ESP01 | P9 | HDR-10X1/2.54 | 1 |
| 3 | RLY | P4 | HDR-4X1/2.54 | 1 |
| 4 | ULTRASC | P5 | HDR-4X1/2.54 | 1 |
| 5 | PIR/TEM | P6 | HDR-4X1/2.54 | 1 |
| 6 | SERIAL | P2 | HDR-4X1/2.54 | 1 |
| 7 | LED_SEL | P3 | HDR-3X1/2.54 | 1 |
| 8 | 220v | P7 | HDR-3X1/2.54 | 1 |
| 9 | JP TX-IO2 | P1 | HDR-3X1/2.54 | 1 |
| 10 | PWR | H2 | HDR-5X1/2.54 | 1 |
| 11 | 1k | R1 | AXIAL-0.3 | 1 |
| 12 | ONOFF | LED1 | LED-3MM/2.54 | 1 |
| 13 | 220V | U3 | KF301-2P-5.0MM | 1 |
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