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2.The process supports design scales of 300 devices or 1000 pads

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STD JLINK_OB_UART

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Mode: Editors' pick

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Update time: 2016-06-14 09:40:45
Creation time: 2016-06-14 09:38:10
Description
JLINK_OB with Visual COM
Design Drawing
schematic diagram
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PCB
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ID Name Designator Footprint Quantity
1 USB_MICROB_PLUG JP1 MICRO-B-RA-SMT 1
2 22 R1,R2 R3 2
3 LM1117-3.3 U2 NONE 1
4 100n C1,C2,C3,C4,C5,C6,C7 C1 7
5 RED D1 LED3MM 1
6 GRN D2 LED3MM 1
7 1k R3 R3 1
8 680 R4 R3 1
9 10k R5,R11 R3 2
10 100 R6,R7,R8,R9,R10 R3 5
11 STM32F072CBT6 U1 NONE 1
12 HDR2X4 P1 HDR2X4 1
13 SIP4 P2 HDR1X4 1

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