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2.The process supports design scales of 300 devices or 1000 pads

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STD FED Tester

License: GPL 3.0

Mode: Editors' pick

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Update time: 2021-03-25 23:49:48
Creation time: 2021-03-22 23:49:13
Description

FED

Design Drawing
schematic diagram
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PCB
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ID Name Designator Footprint Quantity
1 SS12D07VG5 1WIRE_ON_OFF,IGNITION_SW,10_16,9_16_DIN4_EXT0_62_PC3_SW,9_16,10_16_DIN5_INT0_64_PC8_SW,LOOP,7_14_DIN2_SW,12_16,8_14_DIN6_EXT1_63_PC9_SW,12_16_DIN3_INT1_65_PC6_SW,T4/IBUTTON,8_14 SW-TH_SS12D07VG4 13
2 PAD_TERMINAL 15/16,11/16,16/16 CON_PAD_ROUND_32MIL 3
3 78M05 U1 TO-252-2_L6.5-W6.1-P4.58-LS10.0-TL 1
4 CONN-TH_2P-P5.00 CAN,DC,RS232 CONN-TH_2P-P5.00 3
5 0805G (Green) IGNITION_LED,5_14_DOUT2_CSIPOG LED0805-RD 2
6 0805G (Red) 8_16_DOUT1_BLOKKOLAS LED0805-RD 1
7 0805G (Yellow) 6_14_DOUT3_INDEX LED0805-RD 1
8 SEW_HOLE-SMALL 7/16,1/14,3/16,3/14,4/14,8/16,5/14,6/14,10_14_SPEAKER+,4/16,11/14,12/14,1/16,IBUTTON_DATA,IBUTTON_GND,RFID_ANT1,RFID_ANT2,2/14,9_14_SPEAKER-,5/16,6/16,10/14,9/14,7/14,9/16,10/16,12/16,8/14 SIMPLE_HOLE_SM 28
9 Coector DC POWER_JACK 12-4V,12-2V,12-3V,12-1V POWER_JACK_SLOT! 4
10 DS18B20 T2,T3,T4,T1 TO-92-3_L4.9-W3.7-P1.27-L 4
11 20K 4_16_AIN1_P,11_14_AIN2_P,12_14_AIN3_P,8/14_SZONDA,10/16_SZONDA,12/16_SZONDA,9/16_SZONDA RES-TH_RK09D1130C2P 7
12 10K R3,R2,R4,R1 R0805 4
13 0.1u C2,C3,C7,C9,C5 C0805 5
14 0.22u C1 C0805 1
15 RJ11_C11362 RJ4,RJ3,RJ2,FED RJ11-TH_C11362 4
16 NE555DR U5,U3,U2,U4 SOIC-8_L4.9-W3.9-P1.27-LS6.0-BL 4
17 10nF C6,C10,C8,C4 C0805 4
18 RJ9 U6,U7 RJ9 2
19 1k R7,R5,R6,R8 R0805 4

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