Editor Version ×
Standard

1.Easy to use and quick to get started

2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

Profession

1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

4.For enterprises, more professional users

Ongoing

STD Current mode boost converter

License: Public Domain

Mode: Editors' pick

  • 655
  • 0
  • 0
Update time: 2021-06-14 12:52:05
Creation time: 2021-06-14 12:10:53
Description
A current mode boost converter is a type of boost converter in which the **peak switch current limit during the on-time is controlled** in each cycle. This is done by sensing the switch current, adding a ramp to it and comparing it to the error signal generated by an error amplifier. This comparison leads to the generation of reset pulses which help generate the required PWM signal. This curcuit takesin 10V and outputs 35V at over 1A. ![Screenshot 320.png](//image.easyeda.com/pullimage/d6IfbfhJnxAyBXOWX41aHKGG9NtpbCTMfkVNsgEx.png) A close up of the output voltage looks like this: ![Screenshot 330.png](//image.easyeda.com/pullimage/29whET0AVtoJaDXRRXEOdSF8biJAEJ66gXOfaSWG.png) The switch current looks like this: ![Screenshot 321.png](//image.easyeda.com/pullimage/PpQSb0aKcMfaC862i8lFWJFrSVY0TNXzkg51ZBJv.png) and the inductor current looks like this: ![image.png](//image.easyeda.com/pullimage/lHt07AoCoL2w6B3OPYo6xqpVxaovh3cYJhBRZDKj.png) The switch current is sensed using a current sensing resistor. The voltage drop across this resistor is sensed. ![Screenshot 323.png](//image.easyeda.com/pullimage/5TsmHsprQEVaU7ENTmnf9R2B0SZhJLCXm2uynZt4.png) In order to **prevent subharmonic oscillations**, a ramp is added to the voltage generated from the switch current (the parameters of the ramp waveform are not calculated and are selected arbitrarily, but the circuit works fine none-the-less): ![Screenshot 324.png](//image.easyeda.com/pullimage/IX9ReFNfXvDVP0OJwANVKAiOKdhFHBBwmJ108c00.png) ![Screenshot 325.png](//image.easyeda.com/pullimage/zegtQjOibeWSFcDSoOH4LDzKGNWY31rkkqVjCvc8.png) This ramp waveform is compared with an error signal in order to generate reset pulses, which are fed to an op-amp based SR latch. The clock pulses set the SR latch while the reset pulses from the comparator reset the SR latch, thus creating a PWM signal. ![Screenshot 326.png](//image.easyeda.com/pullimage/9w3RQ0MbIJuwTeGiuck1A1qD9vptCaWuUXHjdYZx.png) ![Screenshot 328.png](//image.easyeda.com/pullimage/soCzNK2R1zGOncDtD52LudOUH4sVWCMVqGx9UEPl.png) Vn009 : PWM signal Vn012: Set pulses from clock(green) vn008: Reset pulses from comparator(blue) ![image.png](//image.easyeda.com/pullimage/5g1QklJSC794UU4y5y5YAfrnxoiDGRASNmmXd3qL.png) This is how the required PWM signal is generated. **The efficiency of the circuit is 92.46%** ![Screenshot 329.png](//image.easyeda.com/pullimage/kap0Raex2x0lO8XyWUMM8vASyhWMpSwNQ1VcxQaN.png)
Design Drawing
schematic diagram
1 /
PCB
1 /
The preview image was not generated, please save it again in the editor.
Project Attachments
Empty
Project Members
Related Projects
Change a batch
Loading...
Add to album ×

Loading...

reminder ×

Do you need to add this project to the album?

服务时间

周一至周五 9:00~18:00
  • 0755 - 2382 4495
  • 153 6159 2675

服务时间

周一至周五 9:00~18:00
  • 立创EDA微信号

    easyeda

  • QQ交流群

    664186054

  • 立创EDA公众号

    lceda-cn