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STD Quasi Low-Dropout High Ripple-Rejection Linear Regulator

License: Public Domain

Mode: Editors' pick

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Update time: 2021-08-12 05:21:26
Creation time: 2021-04-19 09:50:50
Description
This is an LTspice simulation of a discrete Quasi Low-Dropout High Ripple-Rejection Linear regulator that I designed. This circuit has a dropout voltage of 1V at 1A of load current and is optimised to have a ripple rejection of over 80dB at 100kHz, with the intention of using it along with a switching tracking pre-regulator. (Interactive everycircuit simulation: https://everycircuit.com/circuit/5419103516622848/high-ripple-rejection-linear-regulator . Note, the everycircuit setup is slightly different from the LTspice setup.) The circuit works by controlling the base current of Q1 by manipulating a constant current sink, made by the BJTs Q3 and Q4. This control scheme has the advantage over ordinary discrete voltage regulators in that the op amp can be powered by a fixed low-voltage supply (like 5V) and still output a voltage greater than 5V, as the series pass transistor is not directly driven by the output of the op amp. **LTspice simulation results:** ++12.000V output for a 15V input with an input ripple of 500mVpp @ 100kHz++ ![Screenshot 219.png](//image.easyeda.com/pullimage/Qug4dUv9s4QInp5kuSUiLlziy5cm28R1KJAxzybz.png) ++Output noise
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Project Attachments
Order File name Download times
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TL072.301

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2

Lin.asc

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