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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD (M) Dual Env

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Update time: 2020-02-23 15:01:37
Creation time: 2020-02-11 21:02:38
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ID Name Designator Footprint Quantity
1 1N4148 D1,D2,D3,D6,D5,D4 DO-41 6
2 470k Log RPOT1,DPOT1,APOT1,APOT2,DPOT2,RPOT2 POT-0.1 6
3 10K REL1,REL2 POT-0.1 2
4 2.2u C3,C6 CAP-E-S 2
5 2N3906 Q1,Q2 TO-92 INT 2
6 20k R2,R7,R9,R18,R44,R35,R33,R28 R-0.4 8
7 1M R1,R8,R34,R27 R-0.4 4
8 33k R5,R31 R-0.4 2
9 5k6 R6,R32 R-0.4 2
10 100k R3,R4,R11,R10,R21,R23,R26,R24,R15,R41,R50,R52,R47,R36,R37,R30,R29,R49 R-0.4 18
11 10k R14,R17,R13,R39,R43,R40 R-0.4 6
12 1k R20,R25,R51,R46 R-0.4 4
13 22k R12,R38 R-0.4 2
14 470 R22,R19,R16,R42,R45,R48 R-0.4 6
15 1n C1,C2,C5,C4 CAP-C-0.1 4
16 CD4001BE U2,U7 DIP-14_SOCKET 2
17 CD4066 U3 DIP-14_SOCKET 1
18 LM324 U1,U6 DIP-14_SOCKET 2
19 TL074 U5 DIP-14_SOCKET 1
20 TL072 U4 DIP-8_SOCKET 1
21 100n C9,C8,C7,C18,C14,C10,C11,C12,C13 RAD-0.1 9
22 10u C17,C19,C15 CAP-E-M 3
23 100u C16 CAP-E-M 1
24 Power P1 DIP-2X5P-2.54MM-M 1
25 Trig 1 J1,J5 JACK-0.1 2
26 PWM CV 2 J3,J2,J4,J8,J6,J7 JACK-0.1 6

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