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STD 8088 Core
License: Public Domain
Mode: Editors' pick
- 2
Update time：
2022-04-24 11:27:35
Creation time：
2015-12-07 15:31:49
Description
This schematic contains the core CPU module for a 8088 in minimal mode.
It exposes the data and address bus, IO/M, RD, WR, RDY1, CLK and PCLK.
Design Drawing
schematic diagram
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 4.7uF | C1 | CAPACITOR | 1 |
| 2 | 10k | R1 | R3 | 1 |
| 3 | 1N4148 | D1 | DO35-7 | 1 |
| 4 | 8284A | U1 | DIP18 | 1 |
| 5 | XTALfast | Q1 | CRYSTAL | 1 |
| 6 | 8088 | U2 | DIP40 | 1 |
| 7 | 74LS373 | U4,U5,U6 | DIP20 | 3 |
| 8 | 74LS245 | U3 | DIP20 | 1 |
| 9 | SPST_OFF | S1 | TACTILE-PTH | 1 |
| 10 | P125-1136A0BR116A2 | J1 | H2X36-2.54 | 1 |
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