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2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

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1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

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STD lm3914

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Update time: 2020-09-25 20:02:12
Creation time: 2020-08-19 21:08:22
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ID Name Designator Footprint Quantity
1 IRF7304 Q3,Q4,Q5,Q2,Q1 SOIC-8_L4.9-W3.9-P1.27-LS6.0-BL 5
2 1k RR2 R_AXIAL-0.3 1
3 4-5k RR1 R_AXIAL-0.3 1
4 470mF 25v C3 CAP-D10.0×F5.0 1
5 100nf C2,C1 C0805 2
6 BD237 Q6 TO-126F-3L_L8.0-W3.2-P2.30-L 1
7 LM3914 U1 DIP-18_L23.0-W6.5-P2.54-LS7.6-BL 1
8 10k R8,R9,R12,R13,R16,R17,R20,R21,R24,R5 R0805 10
9 2k R10,R11,R4,R15,R18,R19,R22,R23,R6,R7,R14 R0805 11
10 20k R3 R0805 1
11 1k R1 R0805 1
12 2.2k R2 R0805 1

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