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2.The process supports design scales of 300 devices or 1000 pads

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2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

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STD SeqPenta

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Update time: 2021-03-16 19:33:37
Creation time: 2019-07-08 10:21:40
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ID Name Designator Footprint Quantity
1 SW OFF-ON-OFF STEPS P2 PLS-3 1
2 4017D U1 SO16 1
3 2N7000 Q1,Q2,Q4,Q5,Q6,Q7,Q8 TO-92(TO-92-3)-2.54 7
4 100k R7,R1,R2,R3,R4,R5,R6,R8,R9,R10,R11,R12,R14,R15,R17 1206 15
5 Clock IN XP2 PLS-2 1
6 Reset XP1 PLS-2 1
7 CD40106 U2 SOIC-14_150MIL 1
8 1N5818RLG D1,D2 DO-41 2
9 POT B100K q5 P3 PLS-3 1
10 POT P4,P5,P6,P7 PLS-3 4
11 100uF C7 CAP-D6.3XF2.5 1
12 10uF C13,C5 CAP-D6.3XF2.5 2
13 15pF C1 CAP_PF 1
14 LED gelb 3 mm LED2,LED1,LED3,LED4,LED5 LED-3MM 5
15 100n C4,C2,C6,C9,C10,C11,C12 1206 7
16 LM2931AZ-5.0 U3 TO-92_MOLDED_NARROW 1
17 HEADER_5X2 C3 IDC10-BLK 1
18 2.2k R13 1206 1
19 330R R16 1206 1
20 10R R18,R19 1206 2
21 OUT XP3 PLS-2 1
22 LM358DR2G U6 SOIC-8 1

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