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STD LM13700 test jigs
License: Public Domain
Mode: Editors' pick
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Update time：
2021-03-30 14:24:48
Creation time：
2017-03-16 10:28:04
Description
Some simple test jigs from the TI datasheet for the LM13700.
The EasyEDA spice symbols LM13700_TI.1 and LM13700_TI.2 both use the original National Semiconductor subckt (now hosted by TI) but the pin connections of each symnbol are mapped onto each of the two devices in the 16 pin DIP (or SOIC) package.
Product page:
http://www.ti.com/product/LM13700
Datasheet:
http://www.ti.com/lit/ds/symlink/lm13700.pdf
Spice model:
http://www.ti.com/lit/zip/snom267
Note however, that the TI subckt does not model the distortion of the input stage as the differential input voltage swing increases!
For background information on the OTA that forms the core of the LM13700, search for:
ca3080-a.pdf
an6668.pdf
Design Drawing
schematic diagram
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LM13700 VCA test jig
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LM13700 VCF test jig
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LM13700 VC floating resistor test jig
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | PULSE(-1V 1V 0s 1us 1us 499us 1ms) AC 1 0 | VIN | 2P-5.0 | 1 |
| 2 | 15V | VPOS,VNEG | 2P-5.0 | 2 |
| 3 | 10k | RIN,R4,R10,RA | NONE | 4 |
| 4 | 5.1k | R2,R4 | NONE | 2 |
| 5 | PULSE(1.5V 2.5V 0s 15ms 1us 1ps 15ms) | V_AMP_BIAS | 2P-5.0 | 1 |
| 6 | 15k | R_ABIAS | NONE | 1 |
| 7 | 800p | C1,C2 | RAD-0.1 | 2 |
| 8 | 1k | R1,R3,R8,R9 | NONE | 4 |
| 9 | 20k | R5,R6,R7 | NONE | 3 |
| 10 | V=V(SWEEP,VEE) | B1 | NONE | 1 |
| 11 | LM13700_DS | U1,U2,U3 | PDIP16 | 3 |
| 12 | SIN(0 10 1k) AC 1 0 | VIN | 2P-5.0 | 1 |
| 13 | 15 | VPOS,VNEG | 2P-5.0 | 2 |
| 14 | SIN(1 14.5 50) | V_AMP_BIAS | 2P-5.0 | 1 |
| 15 | 30k | R1,R_ABIAS,R_DBIAS,RIN | NONE | 4 |
| 16 | 5k | R2 | NONE | 1 |
| 17 | 1K | RTRIM | RES-ADJ_3386P | 1 |
| 18 | 100m | VIN | 2P-5.0 | 1 |
| 19 | 5 | V_AMP_BIAS | 2P-5.0 | 1 |
| 20 | 100k | RR1,RR2,R12,R13 | NONE | 4 |
| 21 | V=-V(INP) | B1 | NONE | 1 |
| 22 | V=-V(RP,RN)/I(VIN) | B2 | NONE | 1 |
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