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1.Easy to use and quick to get started
2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
4.For students, teachers, creators
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1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
3.More rigorous design constraints, more standardized processes
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STD tugas digital clock
Mode: Editors' pick
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Update time：
2021-12-18 18:08:58
Creation time：
2021-12-18 15:23:57
Description
TUGAS
Design Drawing
schematic diagram
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 10uf | C1,C2 | CAPACITOR 10UF | 2 |
| 2 | SW-SLIDE-SPDT_(9040-TH) | CONTROLJAM,CONTROLMENIT | SW-SLIDE-SPDT-9040-TH | 2 |
| 3 | 7_segmentos_display_sevensegment_2,3_inches_70mm | DETIK,DETIK.,JAM,JAM.,MENIT,MENIT. | SEVENSEG_7_SEGMENT_2.3_INCHES_70MM | 6 |
| 4 | pinheader2pin | J2 | PINHEADER2PIN | 1 |
| 5 | LED 5MM | LED2 | LED5MM | 1 |
| 6 | 10k | R2 | R3 | 1 |
| 7 | 74192 | RD1,RD2,RJ1,RJ2,RM1,RM2 | DIP16 | 6 |
| 8 | NE555N | U1 | NE555-DIP | 1 |
| 9 | Resistor variable | U2 | RESISTOR VARIABLE | 1 |
| 10 | 7447 | U4,U6,U9,U12,U15,U18 | 7447 | 6 |
| 11 | SN7408 | DD1 | DIP14 | 1 |
| 12 | SN7404 | DD2 | DIP14 | 1 |
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