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2.The process supports design scales of 300 devices or 1000 pads
3.Supports simple circuit simulation
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1.Brand new interactions and interfaces
2.Smooth support for design sizes of over 5,000 devices or 10,000 pads
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STD Digital Design Project#2
Mode: Editors' pick
- 0
Update time：
2020-02-08 03:15:13
Creation time：
2019-11-21 13:51:40
Description
Parallel IO Chip
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | bar led | U9,U5,U10 | BAR LED | 3 |
| 2 | DIP switchEI-08 | DIP1,DIP3 | DIP-8-2.54MM | 2 |
| 3 | 10k ohm | RN1,RN6,RN5 | RES-ARRAY-SMD_16PIN-L4.20-W1.75-PITCH0.50 | 3 |
| 4 | 330 Ohm | RN3,RN2,RN4 | RES-ARRAY-SMD_16PIN-L4.20-W1.75-PITCH0.50 | 3 |
| 5 | 74AC00MTC | U3,U2 | TSSOP-14 | 2 |
| 6 | SN74HC541N | U8,U7,U4 | DIP-20 | 3 |
| 7 | SN74HC540N | U6,U1 | DIP20 | 2 |
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