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STD RC2014-Z180LinearMemory_v2
License: Public Domain
Mode: Editors' pick
Cloned from RC2014-Z180LinearMemory
- 0
Update time：
2020-11-12 10:01:32
Creation time：
2020-11-06 09:31:50
Description
This is a card for a Z180-CPU for the RC2014 (2x40 bus). It offers 512KByte RAM (upper - starting at 8.0000h) and 512KByte ROM (lower - starin at 0.0000h).
The Version contains connectors for the address lines A16, A17, A18 and A19, for the Refresh-Line. This module can be used with other Z180 modules.
Copied from user "Marten Feldtmann"
Improving to REV 2.0
Improvement design started: 6th Nov 2020
Improvement design finisher: 13h Nov 2020
Hopefully you gyus enjoy this updated version!
Design Drawing
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 100nF | C5_139 | CAP-TH_L6.0-W6.0-P2.54-D1.0 | 1 |
| 2 | 4k7 | R1-4K7 | AXIAL-0.3 | 1 |
| 3 | SST39SF040-70 | ROM_512X8 | DIF32-MSK | 1 |
| 4 | Header-Male-2.54_1x10 | P1-HEADERSIGNALS | HDR-10X1/2.54 | 1 |
| 5 | 100nf | C1_ROM,C3_RAM,C2_BUS | RAD-0.1 | 3 |
| 6 | 74HCT139 | U2-HCT139 | DIP16 | 1 |
| 7 | Bus RC2014/80 | U3 | HDR-2.54-19-2X40P | 1 |
| 8 | AS6C4008-55SIN | RAM_512X8 | DIL32 | 1 |
| 9 | 1A | F1 | FUSE-TH_BD2.7-L7.3-P11.30-D0.6 | 1 |
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