Editor Version ×
Standard

1.Easy to use and quick to get started

2.The process supports design scales of 300 devices or 1000 pads

3.Supports simple circuit simulation

4.For students, teachers, creators

Profession

1.Brand new interactions and interfaces

2.Smooth support for design sizes of over 5,000 devices or 10,000 pads

3.More rigorous design constraints, more standardized processes

4.For enterprises, more professional users

Ongoing

STD How to use basic elements of EasyEDA copy

License:

Mode: Editors' pick

Cloned from How to use basic elements of EasyEDA

  • 621
  • 0
  • 0
Update time: 2018-09-24 13:19:18
Creation time: 2018-09-24 13:19:11
Description
To learn more, see The EasyEDA tutorial: https://easyeda.com/Doc/Tutorial/ See also the Simulation Quickstarter: https://easyeda.com/project_view_Simulation-Quickstarter_iLN8usOaw.htm **To learn more, see [The EasyEDA tutorial].** [The EasyEDA tutorial]: https://easyeda.com/Doc/Tutorial/ To open simulations from the view window, click on the little green pencil in the upper right then do: `Ctrl+R` Save when prompted and then do `Ctrl+R` again. This project is part of the EasyEDA spice simulation learning resource.
Design Drawing
schematic diagram
1 /
PCB
1 /
The preview image was not generated, please save it again in the editor.
ID Name Designator Quantity Mounted
1 SMCJ7.0CA DBIDIRTVS 1 Yes
2 SIN(3 3 1k) V1 1 Yes
3 1k R1,R2,R4,R5 4 Yes
4 PULSE(0 100 0.25m 1u 1u 1f) VPSPIKE 1 Yes
5 PULSE(0 -100 0.75m 1u 1u 1f) VNSPIKE 1 Yes
6 SP1003_01DTG D1 1 Yes
7 0.1 I1 1 Yes
8 Voltmeter VM3,VM2,VM1 3 Yes
9 Ammeter A2,A1,THRUFUSE,A_VCC,A_VEE,UNI,BIDI 7 Yes
10 SPST_OFF S1 1 Yes
11 5 V1 1 Yes
12 10u C1 1 Yes
13 SIN(1.05 1.05 1k 0 0 -90) V1 1 Yes
14 5 R1 1 Yes
15 FUSE F1 1 Yes
16 SIN(0 {Vinpk} 1k) AC 1 V1 1 Yes
17 {rail} VCC,VEE 2 Yes
18 {Rin} R1 1 Yes
19 {Rfb} R2 1 Yes
20 {Voutpk/35m} R3 1 Yes
21 opamp5pEE U1 1 Yes
22 34p C2,C1 2 Yes
23 PULSE(3.3 3.4 1n 1n 1n 1u 10) V2 1 Yes
24 1 ROUT,R1,R2,R6,R4 5 Yes
25 I=0.5*V(vcc)*(TANH((V(vcc)/2-V(in))*10)+1) BINVERTER 1 Yes
26 1.5Meg RFB 1 Yes
27 XTALfast QXTAL1 1 Yes
28 820 RSER 1 Yes
29 5 V1,VCC 2 Yes
30 SIN(0 5 50) AC 1 V1 1 Yes
31 GBJ15005 B1 1 Yes
32 100 LOAD,R3 2 Yes
33 1000u C1 1 Yes
34 1 E1 1 Yes
35 V=-(V(ac1,ac2)^2) B1 1 Yes
36 TLine T1,T2 2 Yes
37 PULSE(0 1 100n 1n 1n 1u 2u) AC 0 V1 1 Yes
38 50 LOAD,SOURCE1,SOURCE2 3 Yes
39 {Rload} R3,R1 2 Yes
40 opamp3pEE U1 1 Yes
41 Fuse X1 1 Yes
42 Optocoupler X2 1 Yes
43 LED D1 1 Yes
44 9 V1 1 Yes
45 1k R1,R2 2 Yes
46 Term X1 1 Yes
47 3D_SW_SPST SW1 1 Yes
48 PULSE(0 10 0 1u) AC 1 0 V1 1 Yes
49 ThermistorEE R3 1 Yes
50 SIN({Vref} {Vinpk} 1k 0 0 90) AC 1 V1 1 Yes
51 {Vcc} VCC 1 Yes
52 {Vee} VEE 1 Yes
53 {Rpullup} R2 1 Yes
54 {Vref} V2 1 Yes
55 compOC5pEE U1 1 Yes
56 I=2*V(in) B1 1 Yes
57 PULSE(-1 1 0 200n 200n 300n 1u) AC 1 0 V1 1 Yes
58 V=V(outdel) B3 1 Yes
59 SIN(5m 5m 1k) I1 1 Yes
60 1G R8 1 Yes
61 1N4001 D1 1 Yes
62 4N25 U1 1 Yes
63 SINE(0 {Vmains} {fmains}) V1 1 Yes
64 PULSE(0 {Ig} {tdel} 10n 10n 0.1m {1/fmains}) I1 1 Yes
65 V=V(gen)*V(softstart) B1 1 Yes
66 V=0.5*(tanh((TIME-5m)*500)+1) B2 1 Yes
67 2N5060EE T1 1 Yes
68 PULSE(0 {Ig} {tdel+0.5/fmains} 10n 10n 0.1m {1/fmains}) I2 1 Yes
69 L0109NT T1 1 Yes
70 BT151_500R_EE T1 1 Yes

Unfold

Project Attachments
Empty
Project Members
Related Projects
Change a batch
Loading...
Add to album ×

Loading...

reminder ×

Do you need to add this project to the album?

服务时间

周一至周五 9:00~18:00
  • 0755 - 2382 4495
  • 153 6159 2675

服务时间

周一至周五 9:00~18:00
  • 立创EDA微信号

    easyeda

  • QQ交流群

    664186054

  • 立创EDA公众号

    lceda-cn