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2.The process supports design scales of 300 devices or 1000 pads
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STD UART
License: BSD
Mode: Editors' pick
- 1
Update time：
2021-09-04 17:19:15
Creation time：
2021-04-01 21:52:05
Description
PCB from a project to build a UART from decrite logic, video series works thru the basics of the circuit.
Design Drawing
schematic diagram
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PCB
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| ID | Name | Designator | Footprint | Quantity |
|---|---|---|---|---|
| 1 | 74HCT193 | U1,U3,U5,U7 | SOIC-16_L9.9-W3.9-P1.27-LS6.0-BL | 4 |
| 2 | CAPACITOR0805 | U6,U21,U20,U19,U18,U17,U16,U14,U13,U15,U22,U23,U24,U25 | 0805A | 14 |
| 3 | 74HCT574 | U12 | SO-20_L12.8-W7.5-P1.27-LS10.3-BL | 1 |
| 4 | Transmit | LED1 | LED1206-RD | 1 |
| 5 | Status | LED4 | LED1206-RD | 1 |
| 6 | Receive | LED2 | LED1206-RD | 1 |
| 7 | Osc | OSC1 | OSC FULL CAN DIP14 | 1 |
| 8 | 74HCT164 | U4 | SO-14_L8.9-W3.9-P1.27-LS6.0-BL | 1 |
| 9 | Status | T_FIFO_STATUS2,R_FIFO_STATUS2 | HDR-TH_5P-P2.54-V | 2 |
| 10 | UartExt | UARTEXT | HDR-TH_5P-P2.54-V | 1 |
| 11 | 100K | R1,R11,R2 | 0805 | 3 |
| 12 | 74HCT00 | U2,U8 | SOIC-14_L8.7-W3.9-P1.27-LS6.0-BL | 2 |
| 13 | 74HCT165 | U10,U11 | SO-16_L9.9-W3.9-P1.27-LS6.0-BL | 2 |
| 14 | ReceiveData | R_FIFO_DATAIN1 | HDR-8X1/2.54 | 1 |
| 15 | TransmitData | T_FIFO_DATAOUT2 | HDR-8X1/2.54 | 1 |
| 16 | MainBus | UART_MAINBUS1 | HDR-8X1/2.54 | 1 |
| 17 | UARTCtrl | UARTCTRL | HDR-8X1/2.54 | 1 |
| 18 | 74HCT32 | U9 | SOIC-14_L8.7-W3.9-P1.27-LS6.0-BL | 1 |
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