Combined sample-hold (SH) and peak detector (PD) for measuring the amplitude of ultra-fast (few ns) pulses originating e.g. from SiPMs or PMT photo detectors utilized in nuclear and particle physics. The PCB is laid out as 2-layer board for rapid prototyping. The SH and PD stages are independent and each of them may be omitted if not needed. The SH stage has switchable input polarity, optional preamp bias back-supply through the input connector and two different gains (low/high gain). It can be operated in following modes: 1) Header "Sampling Gate" jumpered to VCC: peak-hold mode with a decay time constant of several microseconds. 2) Sampling gate fed from external logic signal (pin 2 of header "Sampling Gate"). The circuit operates as a true Sample-and-Hold (S+H) device in this case. The SH stage consists of a wide-band differential amplifier and a fast SPDT switch which selects the required signal polarity. Its output is decoupled and dumped through a forward-biased Schottky barrier diode (MMBD770 or similar; the important parameter here is a very low minority-carrier lifetime yielding ultra-fast switch on/off times) onto an integration capacitor. The capacitor's voltage is buffered by an opamp with low bias current, amplified and actively low-pass filtered. The selected opamp is an inexpensive GBP=100 MHz quad opamp TLV3544 (TI). The PD part utilizes the remaining three opamps to drive the storage capacitor through a network of fast Schottky diodes and to isolate this capacitor with its ultra-high input impedance to avoid droop. Furthermore two n-MOSFETs offer a fast reset of the storage cap (t_r>=100ns). The leakage of the capacitor is compensated by bootstrapping the potential between the switching MOSFETs to the capacitor's voltage.