
2-input CMOS NAND Gate
STD2-input CMOS NAND Gate
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Creation time:2018-10-14 08:36:51Update time:2018-11-28 20:44:03
Description
2-input CMOS NAND gate
Design Drawing
schematic diagram
BOM
ID | Name | Designator | Footprint | Quantity |
---|---|---|---|---|
1 | PMOS_D4 | M1,M4 | 2 | |
2 | NMOS_D4 | M2,M3 | 2 | |
3 | PULSE(5 0 0n 1n 1n 10u 20u) | V1 | HDR1X2 | 1 |
4 | PULSE(5 0 0n 1n 1n 5u 10u) | V2 | HDR1X2 | 1 |
5 | 5 | V3 | HDR1X2 | 1 |

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