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RC80 24 Bit Page Decoder

STDRC80 24 Bit Page Decoder

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569
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Mode:Full

License

MIT

Creation time:2020-07-17 13:59:46Update time:2020-07-18 17:30:52

Description

**CAUTION! ENTERING TESTING/VALIDATION **

UPDATE: Added Male 1x8 2.54 headers (GND) for alternate implementation of '688 select. Permits Male Header Jumper Blocks to be employed in lieu of the switch. Either will work.

Add-on card for decoding extended addresses generated by the Z280 and creating convolved chip selects that are placed on RC80 USER pins for consumption by cards that can take advantage of them.

One card set that would benefit from this decoder card: RC80_PRIOPIO V1.0 and V2.0 boards - under development.

Early Specification Notes:

Original concept artist and oversight/guidance person:
Colin MacArthur

"As for the "Page" decoder card for 16 / 24 Bit addresses

My thought were to have 2 x '688 one for A8-A15 and 1 for A16-A24 and a '02 NOR gate to combined and invert...
Each of the '688 would have a set of 8 jumpers and a 9 pin (8 x 10k ) SIP RP...

The High address '688 would output to USR5 (Jumper for Active High or Active Low using on of the '02 as an inverter)
The LOW address '688 would output to USR6 ( Jumper for Active High or Active Low using on of the '02 as an inverter)
And both would go into a '02 and that output would go the USR7 ( Jumper for Active High or Active Low using on of the '02 as an inverter)

On USR5 you would have an output to select a 64k of 16M I/O Page ( z280 I/O Page / etc)
On USR6 you would have an output to select a 256 of 64k I/O Page (z180 / 80186 / etc)
On USR7 you would have an output to select a 256 of 16M I/O Page (z280 / etc)

As each section could be independent, the High '688 & '02 would be optional...

Design Drawing

schematic diagram
PCB

BOM

IDNameDesignatorFootprintQuantity
1SW_DIP-8SW1,SW2DIPSWITCH-082
2High EnableJPH2HDR-1X03-S-M-2.54MM1
3Jumper_1x3JP-USER5,JP-USER6HDR-1X03-S-M-2.54MM2
4Low EnableJPL2,JP-USER7HDR-1X03-S-M-2.54MM2
5100nFC3,C2,C1CAP-RAD-2.54MM3

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