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rele_gar_pit_2

STDrele_gar_pit_2

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Creation time:2019-11-13 18:23:22Update time:2022-02-06 03:50:32

Description

Design Drawing

schematic diagram
PCB

BOM

IDNameDesignatorFootprintQuantity
1Pin 1+5V,+5VC,F1,F2,GND,GND6,IN,K1,K2,MISO,MOSI,OUT,RELEY1,RELEY2,RES,RS,RX,SCK,TXPIN19
20.1C1,C2,C8,C9,C10,C1208056
322C3,C408052
41ufC512061
50.1C6,C7,C1112063

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