You need to use EasyEDA editor to create some projects before publishing
MikeDB
Drawing hollow rectangle on silk screen
posted by MikeDB , 5 years ago. replied by cjohnson , 5 years ago.
1785 9
Meini
I just dont get it, Z-diode not doing its job?
posted by Meini , 5 years ago. replied by andyfierman , 5 years ago.
846 4
icecool2
Moving part from top to bottom layer
posted by icecool2 , 5 years ago. replied by icecool2 , 5 years ago.
2224 4
jcfor3ver
Pathing doesn't recognize connection
posted by jcfor3ver , 5 years ago. replied by andyfierman , 5 years ago.
739 2
jcfor3ver
Autoroute not working
posted by jcfor3ver , 5 years ago.
522 0
Impuls
Problems with exporting DXF format
posted by Impuls , 5 years ago. replied by Impuls , 5 years ago.
671 2
redsunwit
887 1
miggarc
Increase Footprint Manager and Library Manager preview window
posted by miggarc , 5 years ago. replied by mixkef , 5 years ago.
540 3
MR farby
[IN_NEED_OF_HELP]Converting a single schematic from project to PCB
posted by MR farby , 5 years ago. replied by MR farby , 5 years ago.
1609 2
olamide2006
Bottom Layer
posted by olamide2006 , 5 years ago. replied by andyfierman , 5 years ago.
375 3
miggarc
Penalization (or perhaps penalisation) current costs ?
posted by miggarc , 5 years ago. replied by UserSupport , 5 years ago.
989 1
عبد الكريم محمد
SOLDERED TRACK
posted by عبد الكريم محمد , 5 years ago. replied by andyfierman , 5 years ago.
400 4
campo201904
Footprint ICL7135
posted by campo201904 , 5 years ago. replied by campo201904 , 5 years ago.
455 2
redsunwit
cannot get expe cted result
posted by redsunwit , 5 years ago. replied by andyfierman , 5 years ago.
788 7
miggarc
Forum Avatar doesn't change
posted by miggarc , 5 years ago.
621 0
koosjr
PCB ordered to be Matt Black but came with no colour
posted by koosjr , 5 years ago. replied by andyfierman , 5 years ago.
3027 25
ds380
Min. Edge Rails limitation
posted by ds380 , 6 years ago. replied by andyfierman , 5 years ago.
4310 4
danielweckert
Transistor doesn't switch in simulation
posted by danielweckert , 5 years ago. replied by andyfierman , 5 years ago.
1062 1
Fred
platted edge design
posted by Fred , 5 years ago. replied by MikeDB , 5 years ago.
1283 4
redsunwit
how to probe voltage in simulation
posted by redsunwit , 5 years ago. replied by andyfierman , 5 years ago.
1022 2
cc_CGB
Routing warning message
posted by cc_CGB , 5 years ago. replied by andyfierman , 5 years ago.
538 1
wellinkstijn
can you make a ttl transistor
posted by wellinkstijn , 5 years ago. replied by andyfierman , 5 years ago.
530 5
BdT141
Direct output to JLCPCB not applying $2 deal
posted by BdT141 , 5 years ago. replied by MikeDB , 5 years ago.
831 5
phamduyscb
dont create net name when connect two empty net
posted by phamduyscb , 5 years ago. replied by phamduyscb , 5 years ago.
480 2
aylashiv
How to do V-Cut for Round rectangular PCB?
posted by aylashiv , 5 years ago. replied by aylashiv , 5 years ago.
2118 6
goToTop
你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus-@1x -mockplus-

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice