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Project Last saved timestamp vs creation date
posted by fatboyatdesk , 4 years ago.
359 0
PCB Test Layout for Isolation Routing
posted by fatboyatdesk , 5 years ago. replied by support , 5 years ago.
1151 1
Fabrication Output not working
posted by fatboyatdesk , 5 years ago. replied by fatboyatdesk , 5 years ago.
660 2
Varying a Potentiometer Value during simulation
posted by fatboyatdesk , 5 years ago. replied by andyfierman , 5 years ago.
891 5
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你现在访问的是EasyEDA海外版，使用建立访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程，下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
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