Kicad is an EDA tool not a PCB manufacturer. What effect does: "I add a region of solder to these areas in KiCAD." have when you have had a PCB with this feature added in Kicad, made by a PCB manufacturer?

Yes KiCAD is an EDA tool. I'm aware of that and I design with it. JLCPCB is the PCB manufacturer hence why my question addresses them.  This picture shows an example of what I'm trying to acheive. I add a region of solder in my kiCAD project design where I want this. However, JLCPCB doesn't follow through with it for some reason. That is the issue I am addressing along with getting JLCPCB to add solder to the pads of unpopulated components.

Which PCB manufacturer did you use for the PCBs on your photos and what board finish did you request?

Whst do boards from them look like in areas  where you do not ask for added solder?

@lukenukem Hello ; Thank you for writing your post here. First verse, the solder past is added only during SMT assembly process which should be set during the order placing. Since SMT assembly is related to the soldering of Surface Mount Devices then it could not be performed without the presence of the parts because this process will follow what is inserted in the BOM list which has the list of the design parts then the customer need to select which parts should be soldered through selecting which parts will he order from our SMT parts library, so the soldering process will create the SMT stencil following the P&P file which has the component placement on the board and it is only there where solder past will be distributed.

@lukenukem, Are the boards in your picture wave soldered?

My suspicion is that the PCB in the photo has been wave soldered. You do not get the same buildup of solder using IR (Infra Red) reflow soldering. JLCPCB do not use wave soldering. Instead, as described above, they use solder paste applied by a paste mask and then soldering takes place by the IR Reflow process. Hence it is not possible to produce the desired excess solder technique in an IR Reflow process. It would require a manual post process. There is a useful discussion about the use of excess solder on exposed copper here: [https://electronics.stackexchange.com/questions/440343/why-are-these-traces-shaped-in-such-way](https://electronics.stackexchange.com/questions/440343/why-are-these-traces-shaped-in-such-way) and a practical demo here: [https://www.youtube.com/watch?v=L9q5vwCESEQ](https://www.youtube.com/watch?v=L9q5vwCESEQ)

That makes sense - if the tracks were part of the stencil, parts of the stencil could simply be cut away and fall out. Although they could be joined by bridges to maintain stencil integrity...  but because the thin tinning wouldn't add much benefit, then who cares. The alternative would be to add some 0ohm resistors (50mOhm max specified) along the track. In the worst case, this would make total resistance drop by only 1%, but it would add some thermal mass and a larger surface area for heat convection to air and possibly better radiation. Someone should test thermals of that for fun :)