Hello ; If it is possible could you please provide the part reference or the link to its datasheet! Meanwhile, have you tried to place Vias between the Balls, this may help you to route the inner Balls.

@JLCPCBsupport Based on the screenshot it looks like STM32H743XIH6

DATASHEET  [STM32H743XIH6](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32H743XIH6/7915906)<br> <br> [https://www.digikey.com/en/products/detail/stmicroelectronics/STM32H743XIH6/7915906](https://www.digikey.com/en/products/detail/stmicroelectronics/STM32H743XIH6/7915906)

@r13doc Hello Thank you for getting back with a reply. Considering the Datasheet that you have provided,  it looks that the pad to pad spacing in your package TFBGA is 0.4mm which makes the routing of the part possible following this logic : First verse the minimum Pad to track clearance in you case is 0.127mm and not 0.2mm because we are talking here about Balls means Pads without holes as it shows the below image and you can get this from the capabilities webpage : [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities)  To route this part you can use trace width of 0.127mm and this makes it possible : 0.127(spacing) + 0.127(track) + 0.127(spacing) = 0.381 mm < 0.4mm I hope that this is helpful for you, please let us know if you need any further details.

ok, thanks and I need use via to track  -  it is space between via and pad or via and trace is 0.254mm  is minimum ?? Am I right? Thanks

vias (pads)  - with hole

@r13doc About the spacing that you are asking for it has to be the Via to track spacing which is 0.254mm  Just one last note about the clearances, for the THT components the spacing that you need to consider is the spacing for Pads with holes, for the surface mounted parts (as the BGA Package) the spacing that it has to be considered is the spacing for Pads without holes. Anything else just let us know.


I steel have a problem. there is clearence from track to via is 0.232 - 0.236 and JLCPCB technicaly need 0.245mm. Do you have any advice  for solve this problem. ??? My track - 0.127mm.

@r13doc FYI The needed clearance for track to Via is 0.254mm not 0.245mm Maybe running to the multi-layer PCB could be a solution here, if you route your circuit in 4/6 Layers then you can step the track width down to 0.09mm which solve the issue because this will save more spacing of 0.037mm you can find this out through this equation : 0.254 - 0.037 = 0.217 < 0.236


Ok, In JLCPCB for 4/6 layers there min trace width for outer layer - 0.09mm, but for  inner layer still 0.127mm. Can I use 0.09mm Trace width for inner layer (middle 1 and middle 2)?? Thanks..

@r13doc For 4 Layers PCB the thickness of the outer and inner layers is not the same and has to be set depending on the impedance that you are requiring, so that indication of (outer layer) refer to the outer layer selected thickness because this is a parameter that you can select when you order your PCB and it could be 1oz or 2oz etc.. for your setting I see that you select 1oz thickness and this way you get a trace width of 0.09mm for all your 4 layers :) Please feel free to Email our support team through [support@jlcpcb.com](mailto:support@jlcpcb.com) for confirmation. Thank you and good luck

ok , Thanks. You are the best!!!