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CD4081BM/TR AND gates keep mulfunctioing
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eslipp 1 year ago
Hi I have designed a circuit that contains several AND gates (HGSEMI CD4081BM/TR). When I got the circuits I tested most of them and all was OK, but after assembling my system (including external switches + wires) I have 4 out of 65 gates failing. is several cases, I tested the same card several times and at some stage the malfunction started. I have several cases where e.g. input 1 is 0V, input 2 is +5 and the output is +5. or the output is constant 1.4 or 1.7V.. in one case, close to the time of malfunction I could feel the gate heating up. Each of the inputs for these gates is driven by a toggle switch (single poll, double throw type limit switch) wite the N.C connected to ground and N.O to 5V. All input voltages are not allowed to be floating. I am afraid I have some spiking effect or similar issue. I wonder if you ever encountered such issues.
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andyfierman 1 year ago
"Each of the inputs for these gates is driven by a toggle switch (single poll, double throw type limit switch) wite the N.C connected to ground and N.O to 5V. All input voltages are not allowed to be floating." If you have no pullup or pull down resistor on each switched input, in the instant between the NC contact opening and the NO contact closing - or vice versa - those inputs are momentarily floating so the gate inputs and therefore outputs may be indeterminate. "I am afraid I have some spiking effect or similar issue." Without sight of your project it is not possible to make definite comments but if you have insufficient supply decoupling or a poor PCB layout then there is scope for power or signal integrity problems.
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eslipp 1 year ago
Thanks andyfierman ! PCB design is as simple as it gets- input using male headers (wire connected to toggle switch), AND gates and output. have to say this is my first design so I am sure it is not flawless.. I used no pull up/down resistors - do I have to use those with CMOS ?     1. is it really an issue if the input is momentarily undefined ? is the chip that sensitive ?     2. Looking online I see people use pull down to tie the input to VSS. What resistor value is recommended ? my project homepage link is [https://oshwlab.com/eslipp/ver-4_fixed](https://oshwlab.com/eslipp/ver-4_fixed)<br> <br> and the "open in editor" link is : [https://easyeda\.com/editor\#cmd=new\_schematic\,cmd\_for\_project=1b7a50f2fc2946fa8bd966abc9108f46](https://easyeda.com/editor#cmd=new_schematic,cmd_for_project=1b7a50f2fc2946fa8bd966abc9108f46)<br> <br> <br>
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andyfierman 1 year ago
I have had a quick look at the connectivity but you need to check it very carefully, gate by gate. According to your original post and your schematic, you appear to be running the chips from a VDD of +5V: "...input 2 is +5 and the output is +5..." and a  VSS of -5V: ![image.png](//image.easyeda.com/pullimage/dUiyBftW2JlagsInDUZRzZuC8MHqoSDH4TDwASX3.png) but you are supplying inputs switched between of 0V and 5V:  "...the N.C connected to ground and N.O to 5V. " The logic inputs for a CMOS gate must essentially be equal to VSS to VDD. For a CMOS gate supplied from +/-5V then a 0V input is exactly mid swing so the output will be indeterminate. You also have no power supply decoupling. See: [https://u.easyeda.com/forum/topic/UPDATED-Power-supply-decoupling-and-why-it-matters-30a39d0a77f34d5d8dc77e37c035b3d3](https://u.easyeda.com/forum/topic/UPDATED-Power-supply-decoupling-and-why-it-matters-30a39d0a77f34d5d8dc77e37c035b3d3)<br> <br> The supplies to your switches appear to come from somewhere other than your logic board so there will be inductive loops in your wiring that can pick up interference. You should supply your switches from the logic board so there should be a 3 pin connector (or at least 3 pins allotted on the connector) for each switch to supply VSS , VDD and the switched input net. The PCB may be about as good as you can get it with only two layers but as a result there is no ground or supply plane to help reducce EMI or crosstalk between traces. You also mentioned a relay card. This may generate EMI which could disrupt operation of the AND gates through the interconnecting wires and tracks.
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eslipp 1 year ago
Thanks for your time and helpfull remarks ! Indeed, this is my first design ever. I have good CMOS background and some PCB background but never actually designed anything.. \- My net naming is not good\. actually the "\-5V" net is connected to ground and the "VCC" net is at \+5V \(I use a PC power supply for that\) \- I definitely have no decoupling\. I need to read more about that\.\.     As for the connections - I am quite sue that is OK.     The 3 header connector in the bottom-center of my drawing has 3 inputs - two for power supply (GND and +5)  feeding VSS and VDD of all AND gates,     and the third from an "Enable"  limit switch (SPDT) linked to GND (N.C)  and +5V (N.O). That "Enable" pin is connected to one of the inputs in each channel of each AND.     while the second input of each AND is connected to one of card input headers (also switched with SPDT as above) .  So the output is HIGH only if both "Enable" and the     corresponding input switches are pressed. I am sure that the gates that are bad now were good when I just got them. \- As for the outputs \- they are fed as input into another card that drives solenoids\. I made sure to add flywheel diodes there\. those cards  also have several logic gates \(ANDs\, ORs\, inverters\, MOSFETs\) and I have some failures there as well\- again for the same type of AND gates\. I will create a simplified project with only 4 channels for both cards and upload it. Again- Thanks for your time !! <br> ![image.png](//image.easyeda.com/pullimage/5DJdYIGgKTpQ2MVnYNNxE9cK35BfptLb2KvnglZP.png)
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andyfierman 1 year ago
Another effect I forgot to mention is that with simple SPDT switching connected to the input of a gate, as well as transitioning briefly through a floating connection, a toggle from high to low or low to high will suffer contact bounce. This can cause the input to go indeterminate for several ms. The "proper" way to use SPDT switches is to debounce the input by either by using capacitor to ground at the input of a schmitt trigger or (much more relible) use an SR flip flop with the NO contact driving one side and the NC contact the other, as illustrated here: [https://circuitcellar.com/research-design-hub/design-solutions/how-to-eliminate-switch-bounce/](https://circuitcellar.com/research-design-hub/design-solutions/how-to-eliminate-switch-bounce/)<br> <br> In simple unbuffered CMOS AND gates, one floating input may only be a problem if the other input is high. In buffered gates, either input floating with the other input in a high or low state may still cause excessive current flow - and hence power dissipation - through the complementary pair of MOSFETs on each input across the supply. This is a useful overview of unbuffered versons of simple gates: [https://eepower.com/technical-articles/basic-cmos-logic-gates](https://eepower.com/technical-articles/basic-cmos-logic-gates/#) This is a useful apps note about the differeences between buffered and unbuffered gates: [https://www.ti.com/lit/an/scha004/scha004.pdf](https://www.ti.com/lit/an/scha004/scha004.pdf) The HGSEMI CD4081BM is a buffered gate like this (there are no unbuffered versions of the 4081): [https://www.ti.com/lit/ds/symlink/cd4081b.pdf](https://www.ti.com/lit/ds/symlink/cd4081b.pdf)<br> <br> Some other thoughts: When you were testing the boards did you have everything connected up before you power them up or were there connectors left unplugged? What loads are the relays driving? (Voltage? Current? Load type?) Were the loads connected and powered duirng testing?
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eslipp 1 year ago
I need to go into the material you linked and study some more.   I see that bad decoupling is an issue with signal integrity - I did not understand it may cause mulfunction (like in my case- the gate is not responding anymore). anyway adding     0.1uF capacitors for each VDD/VSS pair and another larger capacitor at the PCB level should be easy. \- When testing\, I had the system connected\. there \(should\) be no case of floating inputs\- I checked it with my DVM before powering on\. however\, I had to power on and off several times since the test is too long \(I have 5 organ stops\, each with 40 inputs\, driving 64 solenoids\) \- The solenoid driver card is not using a relay\. it is based on a pull\-down NMOSFET\.  the schematics are here:   [https://easyeda\.com/editor\#id=\|bb932513d85948eba116a89603bf393e\|ac9a4ee8b9fc47b781568e31ca1771cb](https://easyeda.com/editor#id=|bb932513d85948eba116a89603bf393e|ac9a4ee8b9fc47b781568e31ca1771cb) -  The driver cards get their inputs from the stops output (this is already a digital output). since each flute can be driven by one of 3 keys I use an OR gate at the input and then I         use a high current FET to drive the initial 0.2sec and a lower current to keep the solenoid pressed and prevent overheating.      the solenoids are operated by 12V (using the same PC PSU) . Coil resistance is 5.5 ohm. Inductance is not reported by the supplier . the solenoids control air flow to the flutes.     During the test there was one load connected per test -the one that should have been activated for the specific key tested.  I did notice at one of the tests that the solenoid did     not work, then there was some discharge and after that one of the AND gates was hot and then gone. strange that only these go - maybe it's the buffering. Again- I have some homework here. thanks for the inputs- these are all new to me.. ![image.png](//image.easyeda.com/pullimage/vGh6wawQcXO9dO7cdal3WJz6dhLniyEIOdimSlVd.png)
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