Clarification on Capabilities
257 7
RynoAlberts 2 months ago
JLCPCBsupport 2 months ago
Hello ; Thank you for the time taken to post your comment here; Maybe you are committing a small calculation mistake related to the annular ring of the pads which is 1mm - 0.6mm = 0.4mm and not 0.2mm as you mentioned. So I advise you to make the annular ring 0.2mm which means the width will be equal to 0.8mm instead of 1mm and this way you will save more spacing between pads because you will have 0.4mm extra space and the clearance pad to pad will be 0.27mm + 0.4mm = 0.67mm which could be manufactured :) Please check and let us know if this works fine for you or we can look for other way. Thank you and good luck.
RynoAlberts 2 months ago
Good morning, Thank you for your reply. I neglected to also mention in the first post that this will be a 4-layer board. I believe my calculation is correct. ![MinAnRing.JPG](//image.easyeda.com/pullimage/EsLm08IjrK4TWbiTw4bfkQECtv8mb9xhDa6xv0og.jpeg) 0.2mm + 0.2mm + 0.6mm = 1mm overall width. If I make the width of the pad 0.8 mm. It would mean the width of the annular ring is (0.8mm - 0.6mm) / 2 = 0.1mm, which is not supported by JLCPCB. If I make the annular ring 0.13mm, as per the minimum allowable, then the clearance will be, 1.27mm - 0.26mm - 0.6mm = 0.41mm, which is still less then 0.54mm. But my question still remains, if I change the pads to vias, ![1.27Via.JPG](//image.easyeda.com/pullimage/jVRAe8U8SdSYCobmQDKvn6y0RhGfHiBKQ7cYc7VG.jpeg) Then they meet all the criteria and are manufacturable because via's are NOT constrained by the "0.54mm pad to pad" clearance? Can you provide some clarification on the "Pad to Pad Clearance (Pad with hole, different nets)" rule under these circumstances and will changing them to vias resolve my problem? Thank you.
JLCPCBsupport 2 months ago
@RynoAlberts | | | | | --- | --- | --- | | Via to Via clearance(Same nets) | 0.254mm | ![](https://jlcpcb.com/client/image/pcbCapabilities/minimumClearance1.13c6e9c4.jpg) | The clearance that you are considering is related to VIAs of the same nets, I don't think that all the pins are the same net. Via is not the appropriate solution. Could you tell how are you managing to assemble the FPGA to the PCB? regarding the datasheet link that you have shared it seems that the FPGA board could be assembled by a SIL connector.
RynoAlberts 2 months ago
Hi, Thats correct, I will use SIL connectors. 1.27mm pitch. Here are two photos of someone else that has created a similar extensions board for this FPGA. ![DuvGdZiUwAEYI2l.jpg](//image.easyeda.com/pullimage/vMDVAkVmhPD92BUKDvKMYHzkaj8gzWEPvMPMEH48.jpeg) ![DuvGYHLU8AAfllV.jpg](//image.easyeda.com/pullimage/JMgmjJQgqhSAB20MxlYi5uReWB4CK2pVYqFmnnPU.jpeg) Here is the board I have designed so far. ![QuadExtension.JPG](//image.easyeda.com/pullimage/JwPdrmhwp5s7YQ2yqxIuO4s3bCEWbTS6HiOcO8z0.jpeg) The two centre rows of pads are where the 1.27mm pitch SIL connectors will go. I will buy them from LCSC [1.27mm FEMALE HEADER](https://lcsc.com/product-detail/Pin-Header-Female-Header_HOAUC-2343U-140CNG1SNT01_C343630.html).
JLCPCBsupport 2 months ago
Hello ; Sorry but I think that there is a mistake on the capabilities page, which is not updated. Here is the minimum clearance for VIAs and Pads ![clearance.JPG](//image.easyeda.com/pullimage/oORSjMKs5BKaHQgMSVvui4xsIogQBF3VUAl6Ea2v.jpeg) I think that these settings will make the design clear to be produced :) I will confirm this with the technical team on Monday. Thank you for your understanding.