Hi,
Please can you guys help to clarify the following. I'm making a PCB to be manufactured by JLCPCB. It's a breakout board on which I will place a FPGA that has two 40 pin 1.27mm headers on either side, see it [HERE](https://shop.trenz-electronic.de/en/TE0890-01-25-1C-S7-Mini-Fully-Open-Source-Module-with-Xilinx-Spartan-7-7S25-64-MBit-HyperRAM).
The headers on the pcb are pads 1.27mm apart, 0.6mm hole and 1mm width, with 0.27mm clearance between the pads.
![1.27mm.JPG](//image.easyeda.com/pullimage/acm7cq8AXDxlswcreGxHrLs8cFoWNhs3lr84DleE.jpeg)
According to the clearance specification on the capabilities page.
![HoleToHoleDifferentNets.JPG](//image.easyeda.com/pullimage/1R56BZhn5oWLYr1MycoyhYLhiwwkm4H3nZqTOsqy.jpeg)
I meet this requirement as the holes are 0.67mm apart.
![AnnularRing.JPG](//image.easyeda.com/pullimage/dPGdDoM7FFEgQ9LSiGRLuF2pAS7rphnEXkYYrQKc.jpeg)
I meet the minimum annular ring requirement. Min is 0.13mm, mine is 0.2mm.
HOWEVER! There is also this rule...
![PadToPadWithHole.JPG](//image.easyeda.com/pullimage/NuVxNfS9zASU8wijWNRVfGSAQZYTWfkPgr6z5bjz.jpeg)According to this rule my 1.27mm header is not manufacturable...
The frustating thing is that if I simply replace the pads with via's of the same size it is then manufacturable as vias meet all the requirements, this makes no sense... because for all intents and purposes there are no differences in this specific instance between a 1mm/0.6mm via and a 1mm/0.6mm pad. So either I am misinterpreting the capabilites or the rule is not clearly enough defined.
Any advise on this will be appreciated.
Thanks
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Windows
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EasyEDA
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