Clarification on Capabilities
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RynoAlberts 2 months ago
Hi, Please can you guys help to clarify the following. I'm making a PCB to be manufactured by JLCPCB. It's a breakout board on which I will place a FPGA that has two 40 pin 1.27mm headers on either side, see it [HERE](https://shop.trenz-electronic.de/en/TE0890-01-25-1C-S7-Mini-Fully-Open-Source-Module-with-Xilinx-Spartan-7-7S25-64-MBit-HyperRAM). The headers on the pcb are pads 1.27mm apart, 0.6mm hole and 1mm width, with 0.27mm clearance between the pads. ![1.27mm.JPG](//image.easyeda.com/pullimage/acm7cq8AXDxlswcreGxHrLs8cFoWNhs3lr84DleE.jpeg) According to the clearance specification on the capabilities page. ![HoleToHoleDifferentNets.JPG](//image.easyeda.com/pullimage/1R56BZhn5oWLYr1MycoyhYLhiwwkm4H3nZqTOsqy.jpeg) I meet this requirement as the holes are 0.67mm apart. ![AnnularRing.JPG](//image.easyeda.com/pullimage/dPGdDoM7FFEgQ9LSiGRLuF2pAS7rphnEXkYYrQKc.jpeg) I meet the minimum annular ring requirement. Min is 0.13mm, mine is 0.2mm. HOWEVER! There is also this rule... ![PadToPadWithHole.JPG](//image.easyeda.com/pullimage/NuVxNfS9zASU8wijWNRVfGSAQZYTWfkPgr6z5bjz.jpeg)According to this rule my 1.27mm header is not manufacturable... The frustating thing is that if I simply replace the pads with via's of the same size it is then manufacturable as vias meet all the requirements, this makes no sense... because for all intents and purposes there are no differences in this specific instance between a 1mm/0.6mm via and a 1mm/0.6mm pad. So either I am misinterpreting the capabilites or the rule is not clearly enough defined. Any advise on this will be appreciated. Thanks
Comments
JLCPCBsupport 2 months ago
Hello ; Thank you for the time taken to post your comment here; Maybe you are committing a small calculation mistake related to the annular ring of the pads which is 1mm - 0.6mm = 0.4mm and not 0.2mm as you mentioned. So I advise you to make the annular ring 0.2mm which means the width will be equal to 0.8mm instead of 1mm and this way you will save more spacing between pads because you will have 0.4mm extra space and the clearance pad to pad will be 0.27mm + 0.4mm = 0.67mm which could be manufactured :) Please check and let us know if this works fine for you or we can look for other way. Thank you and good luck.
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RynoAlberts 2 months ago
Good morning, Thank you for your reply. I neglected to also mention in the first post that this will be a 4-layer board. I believe my calculation is correct. ![MinAnRing.JPG](//image.easyeda.com/pullimage/EsLm08IjrK4TWbiTw4bfkQECtv8mb9xhDa6xv0og.jpeg) 0.2mm + 0.2mm + 0.6mm = 1mm overall width. If I make the width of the pad 0.8 mm. It would mean the width of the annular ring is (0.8mm - 0.6mm) / 2 = 0.1mm, which is not supported by JLCPCB. If I make the annular ring 0.13mm, as per the minimum allowable, then the clearance will be, 1.27mm - 0.26mm - 0.6mm = 0.41mm, which is still less then 0.54mm. But my question still remains, if I change the pads to vias, ![1.27Via.JPG](//image.easyeda.com/pullimage/jVRAe8U8SdSYCobmQDKvn6y0RhGfHiBKQ7cYc7VG.jpeg) Then they meet all the criteria and are manufacturable because via's are NOT constrained by the "0.54mm pad to pad" clearance? Can you provide some clarification on the "Pad to Pad Clearance (Pad with hole, different nets)" rule under these circumstances and will changing them to vias resolve my problem? Thank you.
Reply
JLCPCBsupport 2 months ago
@RynoAlberts | | | | | --- | --- | --- | | Via to Via clearance(Same nets) | 0.254mm | ![](https://jlcpcb.com/client/image/pcbCapabilities/minimumClearance1.13c6e9c4.jpg) | The clearance that you are considering is related to VIAs of the same nets, I don't think that all the pins are the same net. Via is not the appropriate solution. Could you tell how are you managing to assemble the FPGA to the PCB? regarding the datasheet link that you have shared it seems that the FPGA board could be assembled by a SIL connector.
Reply
RynoAlberts 2 months ago
Hi, Thats correct, I will use SIL connectors. 1.27mm pitch. Here are two photos of someone else that has created a similar extensions board for this FPGA. ![DuvGdZiUwAEYI2l.jpg](//image.easyeda.com/pullimage/vMDVAkVmhPD92BUKDvKMYHzkaj8gzWEPvMPMEH48.jpeg) ![DuvGYHLU8AAfllV.jpg](//image.easyeda.com/pullimage/JMgmjJQgqhSAB20MxlYi5uReWB4CK2pVYqFmnnPU.jpeg) Here is the board I have designed so far. ![QuadExtension.JPG](//image.easyeda.com/pullimage/JwPdrmhwp5s7YQ2yqxIuO4s3bCEWbTS6HiOcO8z0.jpeg) The two centre rows of pads are where the 1.27mm pitch SIL connectors will go. I will buy them from LCSC [1.27mm FEMALE HEADER](https://lcsc.com/product-detail/Pin-Header-Female-Header_HOAUC-2343U-140CNG1SNT01_C343630.html).
Reply
JLCPCBsupport 2 months ago
Hello ; Sorry but I think that there is a mistake on the capabilities page, which is not updated. Here is the minimum clearance for VIAs and Pads ![clearance.JPG](//image.easyeda.com/pullimage/oORSjMKs5BKaHQgMSVvui4xsIogQBF3VUAl6Ea2v.jpeg) I think that these settings will make the design clear to be produced :) I will confirm this with the technical team on Monday. Thank you for your understanding.
Reply
RynoAlberts 2 months ago
Hi, This makes a lot more sense. To be honest, the way the capabilities are being presented at the moment on the "Capabilties" page of the website is not clear and can definately use some improvement, as its very frustrating and time consuming to try and decipher them. And yes, this means the 1.27mm pitch header footprint is fine for manufacturing. Just one question, when you refer to "pad", do you mean both SMD and TH pads? Usually tolerances can be a little tighter when no holes have to be drilled... I look forward to the response from the technical team tomorrow so I can finalize the design. Thank you for your support, its very much appreciated.
Reply
JLCPCBsupport 2 months ago
@RynoAlberts Thank you for the time taken to post all these details here :) Yes maybe it is time to make the capabilities page much more clear for users. We will update it soon and we will arrange it as well. We count on your understanding, thank you and good luck
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