You need to use EasyEDA editor to create some projects before publishing
Error in PCB capabilities ???
1122 6
gemer.rus 4 years ago
Hi everyone. I mistakenly used the wrong size of the vias, 0.3mm / 0.45mm in the two-layer board. But, it was put into production without errors. Also, "Via to Track = 0.254" but I always used 0.152mm and didn’t have problems. "Pad to Track = 0.54mm", but I also always used 0.152mm. What are the actual capabilities of the JLPCB? Thanks for the answer!
Comments
JLCPCBsupport 4 years ago
Hello ; About the JLCPCB checking system capabilities : * Hole to hole clearance : 0.5mm * Via to Via clearance : 0.2mm * Pad to Pad clearance : 0.152mm * Via to Track : 0.254mm * Pad to Track : 0.54mm > Please not also that the Minimum trace width and spacing for Inner layer and Outer layer (1oz) is 5mil (0.127mm) Would you please find more details through the following link : [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities)
Reply
gemer.rus 4 years ago
@JLCPCBsupport Thank you, but you didn’t answer the question. I have motherboards manufactured on the JLPCB, on which VIA ito VIA 0.152mm, and they work perfectly. I even hold one in my hands right now. Why are you talking about 0.2mm if you can do less without any problems?  Also, you did not say anything about 0.3 / 0.45 VIA. In my last order they were made without problems and questions. Why are you writing 0.6mm then? 0.45 and 0.60 are VERY big differences for small boards.
Reply
JLCPCBsupport 4 years ago
Hello , Sorry for this .  The " Pad to Track ≥0.54mm " is wrong . It is waitting to change . The  actual is  Pad to Track ≥0.15mm  , 0.17mm is better .  :)
Reply
JLCPCBsupport 4 years ago
@gemer.rus Soon we will back to you with the link of our official updated capabilities, until that you can ask as in the forum about all your requirements. Thank you for your comment and let us know if we can further assist you.
Reply
gemer.rus 4 years ago
@JLCPCBsupport I got my printed circuit boards, 0.3 / 0.45 holes are made perfectly. I think you should write that this is possible for 2 layers. ![of_qCvUH0yg (1).jpg](//image.easyeda.com/pullimage/Se9q90QHEw9Rb4nLn6bmJjXY8E5PLnr81oV1HdKq.jpeg)
Reply
JLCPCBsupport 4 years ago
Hello ; I'm happy to see you again here with a positive feedback and great result, good design so keep it up and we will update the two layers capabilities ASAP
Reply
Login or Register to add a comment
goToTop
你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus-@1x -mockplus-

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice