For the JLCPCB assembly service can I abut resistors end to end ?
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MikeDB 1 week ago
I.e can the standard silk screen outlines be touching end the end and the component placer have no problems placing the second resistor ?
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andyfierman 1 week ago
For clarity, a couple of screenshots of silkscreen outlines separate and silkscreen outlines overlapping would probably be helpful to the people in JLCPCB. Then they can quickly understand the issue and could give a tick / cross sort of reply. :)
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MikeDB 1 week ago
Here you go.  These are the standard 0805 EasyEDA library symbol. I believe R33 and R62 are fine, I've never met a place that couldn't place them side by side. But some assembly houses have problems with R33 and R34 abutting. Does JLCPCB have any rules on close component placing ? <br> ![image.png](//image.easyeda.com/pullimage/rmaS2i8VOqFKQrLrBbL9vp2bpY3djl3JaY3gSeov.png)
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JLCPCBsupport 1 week ago
@MikeDB Hello Mike ; Kindly respect the minimum distance between two different nets and it will be fine for the assembly. Minimum trace width and spacing | Copper weight | Min. Trace width | Min. Spacing | Patterns | | ------------- | ---------------- | ------------ | -------- | | H/HOZ (Inner layer) | 5mil (0.127mm) | 5mil (0.127mm) | ![](https://jlcpcb.com/client/image/pcbCapabilities/minimumTraceWidthAndSpacing.06fad8fa.jpg) | | 1oz (Outer layer) | 1/2 layers: 5mil (0.127mm)<br>4/6 layers: 3.5mil(0.09mm) | 1/2 layers: 5mil (0.127mm)<br>4/6 layers: 3.5mil(0.09mm) | | | 2oz (Outer layer) | 8mil (0.2mm) | 8mil (0.2mm) | | Any further questions just let me know. ^_^
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MikeDB 1 week ago
Okay that's good.  Some assembly houses have problems with reflow as it pushes solder across the board and you get shorts if the resistors are too close.
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JLCPCBsupport 4 days ago
@MikeDB For the small packages, we advise you to keep a distance between the tiny components to avoid any sort of accident Good luck and thank you for writing to us here.
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andyfierman 4 days ago
@JLCPCBsupport, Please specify a minimum spacing and add this to the JLCPCB Capabilities page. Thanks.
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JLCPCBsupport 2 days ago
@andyfierman @MikeDB Hello, I got a final clarification for minimum distance to keep between components for some packages as it shows the below images : ![139368993_230375261889423_6233181893237607139_n.png](//image.easyeda.com/pullimage/UfeW6KWTeDKqIgYuwJjGqrPRnVgwxk2XmajsfouE.png) ![139537517_886568488837389_1264329226567889731_n.png](//image.easyeda.com/pullimage/pDtYI3lk0cjhQFWSi9MOM7qFoXrZyUK47YowXzjj.png) These parameters will be added to the capabilities page ASAP. Any further details just let me know. Thank you
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MikeDB 2 days ago
Thanks.  I'll go through my designs and see if I've broken any of these. It looks like your process has the same spacing end-to-end as side-to-side.  This isn't always the case elsewhere.
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MikeDB 2 days ago
@JLCPCBsupport  @andyfierman Could you add these spacings to the DRC in EasyEDA ?  It's taking ages to check every component.
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andyfierman 2 days ago
@MikeDB, @EasyEDAsupport
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andyfierman 2 days ago
@UserSupport, Please incorporate these minimum spacings into EasyEDA Design Rules. @JLCPCB, Please include these minimum spacings into the JLCPCB Capabilities page. Thanks.
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UserSupport 1 day ago
@andyfierman @MikeDB It will be implemented at EasyEDA Pro.
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