How to add a capped via to a PCB layout?
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jmgonet 1 week ago
Hi all, I'm designing a new PCB layout which will be quite tight. I would like to use via in pads to simplify my design. To do this without the solder going through the hole I would use copper capped vias, also called blind vias, which now seem to be a quite common design practice. How could I do this in EasyEda? Regards,   Jean-Michel Gonet EDIT: I've changed the category of the post to JLCPCB, as suggested by Andy ![Capped Via vs Normal Via](//image.easyeda.com/pullimage/rRrojw1EpkLeq9bg5OquuhCS3vK2HWsDhaoxegyG.png)
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andyfierman 1 week ago
There is no direct way to specify a capped via in EasyEDA. AFAIK, JLCPCB does not support capped vias: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) However, may I suggest that you change the category of this post to JLCPCB and/or ask Support @ JLCPCB if they can help you.
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JLCPCBsupport 1 week ago
I completely agreen with Andy !  Currentlty  JLCPCB does not support apped vias or blind vias , only makes Through Hole   . ![image.png](//image.easyeda.com/pullimage/MVDT4D7O7LM987QxfiqN51VRevuWPM06KVMpsxC7.png)
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jmgonet 1 week ago
Ok. Well, at least I know of this limitation. Do you believe that you're going to add that capability? Regards,   Jean-Michel
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JLCPCBsupport 1 week ago
Maybe we will add it  in the future . Nothing is impossible !  :0)
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