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How to route TFBGA STM32MP1
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FloH 3 years ago
Hello, For several home projects a try to create a "controller card" with STM32MP151DAC1 with package TFBGA361 to use a lot of input/output. I already have the most important chips in stock. (SOC, RAM, Flash, Ethernet, PMIC and hub USB) Now, I try to test routing between RAM and SOC to determine the routing constraints and see how to place components. Now the issue : TFBGA361's pad (outside) : diameter 0,3mm 1 Center pad to center pad 0,5mm. There is 0.2mm of space left. I try to use 4 layers. Footprint: ![image.png](//image.easyeda.com/pullimage/ja0lJvpQoUhro2W2mpQ6vCGtfHYQax8hsOnYvIQR.png) Now, look at left pads. Outside I can pull out wire directly or use via. But inside (pad in red zone), I can't pull out wire directly. ![image.png](//image.easyeda.com/pullimage/XRLupzrJckek7u70t98uBwBOXaqX84sCEgut8Ym9.png) JLCPCD capabilities to BGA: ![](https://jlcpcb.com/client/image/pcbCapabilities/bga.1bf8eb13.jpg) capabilities with via is 0,2mm to hole and 0,4mm to diameter. capabilities with trace 0.09mm capabilities with spacing  0.09mm There should be 0,27mm spacing to use trace. ![image.png](//image.easyeda.com/pullimage/sER9cZ6iVvuNtZEyjQ2bIxQItZLcI7iClnABxWMJ.png) Via in center don't work. ![image.png](//image.easyeda.com/pullimage/kqx9ttcLYutZQw4EvmPTSaTX2jnFPk0WyqFkk4JD.png) I deduce that routing is possible but how? If pad are via, it's work. Is this going to cause soldering problems with reflow? I have to put a via on each pad to have the same height for each pad? In this case, it doesn't work because I couldn't get the wires out. Are the vias filled with resin to prevent sagging or rising air? ![image.png](//image.easyeda.com/pullimage/SHVU1maSMTYLnXNR0EuMjL6je6G4UYPDBf6UNdrA.png) Do you know how can I route it? Thanks in advance.
Comments
andyfierman 3 years ago
You may get a faster reply if you edit your post to change the **Category** of this topic to JLCPCB. :)
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FloH 3 years ago
Thanks. I had not thought of this category.
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JLCPCBsupport 3 years ago
@FloH Hello Thank you for your question, You already tried the answer in one of your attempts, the VIA idea could be a solution. The needed space to make the trace in between two pads is 0.27mm and your BGA Package doesn't fit for this requirement. I saw in a similar case a user tried the solution of VIA but don't replace all the pad as VIAs or you will face the VIA to VIA spacing clearance issue, I suggest that you modify the package of part and you transform some Pads Columns into VIAs Columns and try to route, do not forget to use exposed VIAs so the VIAs don't get covered by the soldermask and this way you can re-flow the part by yourself. Routing this chip looks challenging :) Please let us know the updates so we can suggest more solutions in order to help you out. Best regards and good luck
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FloH 3 years ago
I ordered the 9 other PCBs because this last card is not routable with these technical manufacturing constraints. Even if I put vias on the 3rd row pads, I can't take out the 4th row pads. It is necessary with lower constraints to pass tracks between pads and use laser via. The manufacturer's routing examples show this clearly. ![image.png](//image.easyeda.com/pullimage/cpnbyk4HHil7Amo7L94SJSGbesO3wEHXCug9PHBp.png) ![image.png](//image.easyeda.com/pullimage/KsEe7cMkdktdLV8w80h0xkRp1kJpFfbRyt5wLeA9.png)
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