Hello ; Thank you for posting your question here. Please make sure that the clearance (outer pad to pad) related to you components is really 0.2mm. If you provide the component reference, we can better assist you. In many DR-QFN parts the outer pads clearance is 0.45mm Your request is totally clear and very well explained, please provide us with the requested information to help you more in this. Thank you.

Hi JLCPCBsupport, my component is MT7688AN. You can found datasheet [here](https://s3-ap-southeast-1.amazonaws.com/mediatek-labs-imgs/downloads/1f9d1b96f0f20242df0e3826fccc9da0.pdf?response-content-disposition=inline%3B%20filename%3DMT7688_Datasheet_v1_4.pdf&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Security-Token=IQoJb3JpZ2luX2VjEDUaDmFwLXNvdXRoZWFzdC0xIkcwRQIhAOADK2ZdeRxT1nXb2u3pBzWKtzYMov4lm9%2BDHzurpw1cAiAdxqj8Mv2K5f1C%2BZyaVqcpj7us%2BTCL4Xhw18g6DEzdxyq%2BAwg%2BEAEaDDQ0OTY5Njk5MjA2NiIMkGQp1pMWcMPhS%2BpMKpsD1vBwHzPjRcGqute7kxC57j4YCMSssyGDMWZDb10K5xhxIaA78FRYvUJ%2FcYVAgX5PXXUGK1HJ6YbPScg5kV0lkkSu4D5Vez6Vk2JzVEFyMiqO9eb5PscRQrciJzQ5tctNQzAG83ged6Ndns0fZrlEC4AO0MVC%2BwqM5JaLexUQao6W4uJFeOolS2GVmmC5PBMv5IqfrjW4xBCL97mGzzZev3Qb9C%2Fe%2BA6I3SZZZH11K1mMWFHysgZVbWFofqcD%2BwxhR0He68dbH0P%2F%2FeD8GAKISV0Xncie6clrfBKlAGQYVJXiNq0SNVNVGqsBQgSJy0JpAQTYoHzMAPP8kJnHVQ3NoihUmDdA21X74aGTRG8%2FeaoQgoWApGA%2FIrjjL727k3h%2FPp9HK7eeDSsDsZJrHs%2FGXaUJEPon8vFGlG%2FsP5SlZ1C8pHtLUXbj4agOEGdpH3zr%2BWpbaMJgvRrjIPlQExM81CDuzwp8rFrlRZMsvrW1kRiEYhsgjP3t6RZFklLHfiubSZGLz0LnDlagOnsp3pvFk7cf7Mbj3%2FnCTf31MNfF4foFOusBXvPlVpS6lHMljSGiEHNTZQvQ58ElyxympdSzbl915j6cR9av%2BxWUDEu2UvT%2FF%2F0MHzv6wbfB9tGzqZAz05HOSTBfai%2B%2BZL3K22eggKLI%2BmcyHSdTvvxb8vUAA7UwmQP%2BOgosKaO3%2FisQvdQB8mEQz%2BZwo5owqnEeyVxXj%2FBrCLeNvIroFD1TaCzJkIF8K2ybkHs9wGVYslVHEocJurXhbobPJxeyBIZP2%2B%2Ft8hcHggExCnS2ju87PNINwju%2FBnogzzZ8iPrLvQsYqasl6jvlYF5RMNEMaoDBE8zASEfQwSalyuMNoTADCBzTKg%3D%3D&X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Credential=ASIAWRNAHRNBNLAO2BVY%2F20200909%2Fap-southeast-1%2Fs3%2Faws4_request&X-Amz-Date=20200909T055740Z&X-Amz-SignedHeaders=host&X-Amz-Expires=600&X-Amz-Signature=1038f0f93c55e27c9ecee8daff71e08dd12f60e1ff7331431a7cfafe6c5857fe). Package Physical Dimensions desicribed in page 43 in section "4.9.2 DR-QFN (12 mm x 12 mm) 156 pins". Few screenschots to minimize your time:  

@iot-hub Hello ; Thank you for the useful information. Regarding the datasheet that you have provided, the pad to pad clearance of the outer line is 0.2mm if we consider the maximum lead width, so if we measure it as follows : The measure of lead pitch (eT) = 0.5mm related to the **B**asic **S**pacing between **C**enters The lead width max (b) =  0.3mm Then the clearance outer line pad to pad is eT - b = 0.2mm For JLCPCB capabilities the clearance trace to pad is 0.127mm and minimum trace width is 0.127mm so in order to route similar component you need a sum of : 0.127 mm + 0.127 mm + 0.127 mm = 0.381mm at least which is not possible in your case. We are sorry that we can't produce this part for you regarding our capabilities. Thank you again for the time taken to write your post here.

You don't need to trace between the outer pads to connect to the inner ones. You can use any other layer (bottom one if it is a two layer board) and then put a via under the body of the component. Like so: 

@iot-hub @ResistanceRoom This could be a solution only if you find a way to route all the inner 76 pads. The part is really tight and it has 19 pads in each of it inner lines which is a total of 76 pads to be routed in a surface of 12 mm x 12 mm. Please to consider the minimum Via diameter which is 0.6mm for single&double layers PCB and the minimum clearance Via to Via which is 0.254mm. so if we make a two lines of Vias for each of the inner lines there will be a sum of 0.6 mm x 10 Vias = 6 mm + 0.254 mm x 9 spacing = 2.286 mm the total space needed is 6 mm + 2.286 mm = 8.286 mm Then if we consider two lines of Vias then we need to take a Via to Via clearance of 0.254 mm Please find more explanation in the below image : 

@ResistanceRoom, @JLCPCBsupport, thanks for you proposal. It's first what I start to did but not finish and asked a question. As I understood - this option is work if in chipset I have possiblility to connect some inner/outer pads like 1 inner ground pin and 1 outer ground pin nearby for example. Need to check this. @JLCPCBsupport, BTW: Returning to BGA requirements. In JLCPCB allowed space between balls - 0,127mm. Minimal trace or clearance are equals the same 0,127mm too. How to trace inner balls in this case or maybe it's some missprint in requirements?

Have this:  via size 0.45/0.25 (4+ layer board requirements) but based on last comment from @JLCPCBsupport looks like not possible to meet to "via to via" requirement, right?

Update from my side. Please see picture below. Looks like I have possibility to make PCB. Legend: Grid size: 10 mil (0.254 mm)  Pad to Pad clearance(Pad with hole, Different nets): 21.25 mil (0.54mm) - looks OK. Pad to Track - 7.87 mil (0,2mm) - looks OK. What is missed? Thanks.

@iot-hub Hi again Good to see the update which looks positive as a result. You wrote : > Pad to Pad clearance(Pad with hole, Different nets): 21.25 mil (0.54mm) - looks OK. You don't have any Pad with hole in your image, so please check, you better use the Pad to Pad clearance | | | | | --- | --- | --- | | Pad to Pad clearance(Pad without hole, Different nets) | 0.127mm |  | About the BGA, that is not different but what we have mentioned is the minimum spacing between balls and if you get a component that reach this clearance than routing it will be through Vias the way you did with your DR-QFN package part and it will be almost something like the following image :  Have you done finished the DR-QFN part? Do you still need any support? Thank you again for your post.

HI @JLCPCBsupport, thank you for you response. \>\> Have you done finished the DR\-QFN part? Do you still need any support? Give me one day plz... I'm in the finish stage. What is better to check: share some screenshots with info or maybe share project to check/validate?

@iot-hub Hello ; You can share the project Ok

Hi @JLCPCBsupport, I copied project and removed all unnecessary part except DR-QFN + one part for text connection. Project available [here](http://www.easyeda.com/iot-hub/dummy-test). Checked in JLCPCB design rules. Looks ok from DRC errors perceptive... but :) 

@iot-hub Hello ; Regarding the method, you are in a good road 

Hi @JLCPCBsupport, I'm really approciated for you help. Thank you very much!

@JLCPCBsupport Sorry to bring this thread back to life but, i really need to ask ... the BGA component i want to use has 30 balls (DSBGA-30 [LM3248TMX/NOPB](https://gr.mouser.com/ProductDetail/Texas-Instruments/LM3248TMX-NOPB?qs=sGAEpiMZZMvAX9OfPh%252B2NR1peTcgfgQpnfR1LLCqh5v8F89FvRYBrw%3D%3D)) how am i supposed to route the inner pads? same for many other 0.4pitch BGA components which are more commonplace day after day. especially with component shortages, sometimes you can find the BGA component easier than its DFN or similar equivalent.

@catech75 Hello Thank you for writing to us here. Considering the part's datasheet, it looks like you are not having enough space to place Vias to help you route the inner balls, if you will use all the balls then maybe you need to create a new footprint for the part, ensure that you use the same balls size and the same spacing but in the new footprint you use exposed Vias instead of pads, this is not a recommended method but stills a solution for such issue. As I mentioned, the Vias should be exposed in order to be able to solder the part. Good luck

@JLCPCBsupport still, minimum via specs are as far as i know 0.40 diameter with 0.20 hole, is that not correct? wouldnt it work if i simply design a multilayer pad 0.27 diameter with a 0.2 hole in it?

@catech75, You can use multilayer pads in place of vias but check the minimum dimensions and spacing of the two on the JLCPCB Capabilities page.