The message is from EasyEDA not LTspice. That message usually means that there is something that EasyEDA does not understand in the net listing of the schematic. Quite often it is caused by some sort of syntax error or a badly constructed part of a circuit that fails to converge. I haven't run it because you haven't posted a link to it but it's possible that the VDC GND netlabel that you have added to the GND net is causing the problem. As described in the section on Avoiding Common Mistakes in the Simulation Tutorial (3) in (2) in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) that is a no-no anyway. Another possibility is that the bases of Q1 and Q4 appear to be connected to each other but not to anywhere else. Looking at your circuit I'm guessing that Q4 is to provide short circuit protection to the Darlington connected pair and so (a) the base should be connected to the junction of Q2 emitter and R2 and (b) the collector and emitter pins should be reversed. Also I note that the collector and emitter pins of Q5 are connected the wrong way round. There are also two questionable aspects of the design: (A) the transient response of your circuit will be unusably slow because it is slugged into glacial timescales by C2 across what should be the collector of Q5; (B) connection the base of Q5 across the short circuit setting resistor is a a bad idea because it will change the load current at which Q4 starts to sink the Darlington pair base current. In the worst case Q1 may clamp the voltage across For more help please post the link to your project. The message is from EasyEDA not LTspice. That message usually means that there is something that EasyEDA does not understand in the net listing of the schematic. Quite often it is caused by some sort of syntax error or a badly constructed part of a circuit that fails to converge. I haven't run it because you haven't posted a link to it but it's possible that the VDC GND netlabel that you have added to the GND net is causing the problem. As described in the section on Avoiding Common Mistakes in the Simulation Tutorial (3) in (2) in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) that is a no-no anyway. Another possibility is that the bases of Q1 and Q4 appear to be connected to each other but not to anywhere else. Looking at your circuit I'm guessing that Q4 is to provide short circuit protection to the Darlington connected pair and so (a) the base should be connected to the junction of Q2 emitter and R2 and (b) the collector and emitter pins should be reversed. Also I note that the collector and emitter pins of Q5 are connected the wrong way round. There are also two questionable aspects of the design: (A) the transient response of your circuit will be unusably slow because it is slugged into glacial timescales by C2 across what should be the collector of Q5; (B) connection the base of Q5 across the short circuit setting resistor is a a bad idea because it will change the load current at which Q4 starts to sink the Darlington pair base current. In the worst case Q1 may clamp the voltage across R2 so far that Q4 cannot turn on enough to control the  Darlington pair base currently. Conversely the base of Q4 may never rise high enough in current limit to turn Q1 on enough to light the LED. It's a nice and tempting idea but not good design practice. A better solution might be to make Q1 and Q4 identical, matched transistors (noting that unlike in real life, in spice all devices of the same part number are absolutely identical unless you edit their model parameters!). Adding a resistor in series with the base of each transistor would help and might allow the use of non matched transistors but will make the current limiting response softer. For more help please post the link to your project.