Questions about the dimensions of two adjacent multilayer (PTH) pads
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andyfierman 8 months ago
Please see the attached image: ![image.png](//image.easyeda.com/pullimage/56UbsP0D0HnguJdEoZypN3lcsGqifuOIhj330lhA.png)
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cjohnson 8 months ago
From: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) **What is the minimum value of A: **The annular ring has to be greater than 3 mil **What is the minimum value of G: **As far as I know, annular rings can intersect. One of our PCB's can either fit a 2.5m or 5mm lead spacing cap: ![image.png](//image.easyeda.com/pullimage/ktXypx5dzMVp4m11muZyyMeadcICsX9O1qqLymLq.png) **What is the minimum value of D:** The minimum drill hole size is 0.2mm **What is the maximum value of D:** The maximumdrill hole size is 6.3mm That's all I can figure out from the website order capabilities website, not sure about the others. Thanks! Colby
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andyfierman 8 months ago
Thanks Colby, I have read all the stuff you pointed out from the JLCPCB capabilities and your image very neatly illustrates the kind of issue this post is intended to resolve. Having seen the problems one or two people have been having with JLCPCB rejecting boards which apparently pass the EasyEDA DRC, I'm looking for some definitive figures from JLCPCB directly.
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cjohnson 8 months ago
@andyfierman For reference, I've now ordered two designs with the caps like this (both passed DRC and JLCPCB approval). I'll be receiving these boards sometime next week.
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andyfierman 8 months ago
Thanks. :)
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MikeDB 8 months ago
Yes I always do that as well with inductors as there are often shortages of particular lead spacings.  So far I've never had a board rejected for it.  \
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andyfierman 8 months ago
I too have had boards made with similar dual footprinting but JLCPCB need to clarify these parameters to avoid anyone else getting into the sort of issues that voltar99 encountered in: [https://easyeda.com/forum/topic/Unethical-Refund-Policy-e6e65112001d41c8b53d8d530fc4abfa](https://easyeda.com/forum/topic/Unethical-Refund-Policy-e6e65112001d41c8b53d8d530fc4abfa) "I recently submitted a clean design to JLPCB.  It passed all of the online DRC checks using JLPCB's default settings...At the factory, the design was rejected because their internal DRC software found some holes that were too close together in a library element."
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andyfierman 8 months ago
* Could someone from JLCPCB support answer my orignal questions please? The thickness of the copper plating is 18 µm. ![Through plating.jpg](https://image.easyeda.com/pullimage/LMyr9ChxkPkQejL3GwEihSRZXclPsBvFFGGPhEdZ.jpeg) but that does not answer the question about what is the **maximum** thickness and the rest of my original questions? Thanks.
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andyfierman 7 months ago
As this is posted as a JLCPCB topic, could someone from JLCPCB please respond? Thanks.
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pcb_Service 6 months ago
Dear Andy, So sorry for the late reply, this is Eunice from JLCPCB. Here is the answer for your question, hope it is useful for you. Any question, just feel free to contact with me. A≥0.13mm,If 2 layer board, A≥0.127mm, If 4&6 layer board, MAX P=0.0127mm MIN G=0.127mm MIN D=0.7mm MAX D= 6.35mm E=0.531mm Best Regard Eunice Yin JLCPCB team
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andyfierman 6 months ago
@pcb_Service, Thanks. :)
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pcb_Service 6 months ago
@andyfierman Dear Andy, This is a type mistake. The minimum D is: 0.2mm
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andyfierman 6 months ago
@pcb_Service, Got it thanks.
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