I have panelized a board, but when I upload the Gerber to JLCPCB, the silk layer overlaps the other panels.
Will this appear on the final panel? How is it possible to remove the Silk print that is outside the board?
![Capture d’écran 2020-12-15 à 14.08.48.png](//image.easyeda.com/pullimage/alsN0j23N6YKBQ7BvYh3QsmMxkHys6jUjBsfCioD.png)
Chrome
87.0.4280.67
OS X
10_14_6
EasyEDA
6.4.7